摘要
本文介绍了一种在传统计算机组成原理实验仪上,开设Cache实验时的主存储器的接口设计方法,并给出了电路和数据通路分析,最后进行了性能比较。
This article introduced a way of interface design of main memory for Cache experiment on a traditional experiment packet of computer organization and architecture. The circuit and data access analysis were presented. Finally, a performance compaison was given.
出处
《实验室研究与探索》
CAS
2004年第4期31-33,共3页
Research and Exploration In Laboratory
