摘要
介绍了一种12位高速、低失真数字/模拟转换器(DAC)的设计原理及其电路结构;着重阐述了去毛刺技术及其应用。采用2μm等平面隔离互补双极工艺模型参数进行了Cadence仿真。结果表明,该12位DAC在高达60MHz数据更新率下具有低于100pV·s的毛刺脉冲面积。
The design principle and circuit structure of a 12-bit high-speed low-distortion digital-to-analog converter (DAC)are described. The technology of deglitching and its implementation are elaborated in particular. Simulation is made using a 2-μm isoplanar isolation complementary bipolar process model. It has been shown that the 12-bit DAC has a glitch pulse less than 100 pV·s at 60 MHz data updating rate.
出处
《微电子学》
CAS
CSCD
北大核心
2004年第3期341-344,共4页
Microelectronics
