In order to minimize the self-heating effect of the classic SOI devices,SOI structures with Si3 N4 film as a buried insulator （SOSN） are successfully formed using epitaxial layer transfer technology for the first ti...In order to minimize the self-heating effect of the classic SOI devices,SOI structures with Si3 N4 film as a buried insulator （SOSN） are successfully formed using epitaxial layer transfer technology for the first time. The new SOI structures are investigated with high-resolution cross-sectional transmission electron microscopy and spreading resistance profile. Experiment results show that the buried Si3 N4 layer is amorphous and the new SOI material has good structural and electrical properties. The output current characteristics and temperature distribution are simulated and compared to those of standard SOI MOSFETs. Furthermore, the channel temperature and negative differential resistance are reduced during high-temperature operation, suggesting that SOSN can effectively mitigate the selfheating penalty. The new SOI device has been verified in two-dimensional device simulation and indicated that the new structures can reduce device self-heating and increase drain current of the SOI MOSFET.展开更多
A damascene structure of phase change memory （PCM） is fabricated successfully with the chemical mechanical polishing （CMP） method, and the CMP of Ge2Sb2Te5 （GST） and Ti films is investigated. The polished surfac...A damascene structure of phase change memory （PCM） is fabricated successfully with the chemical mechanical polishing （CMP） method, and the CMP of Ge2Sb2Te5 （GST） and Ti films is investigated. The polished surface of wafer is analysed by scanning electron microscopy （SEM） and an energy dispersive spectrometer （EDS）. The measurements show that the damascene device structure of phase change memory is achieved by the CMP process. After the top electrode is deposited, dc sweeping test on PCM reveals that the phase change can be observed. The threshold current of array cells varies between 0.90mA and 1.15mA.展开更多
In order to reduce the reset current of cllalcogenide random access memory; a W sub-microtube heater electrode with outer/inner diameter of 260/100nm, which was fabricated with standard 0.184-μm technology, is propos...In order to reduce the reset current of cllalcogenide random access memory; a W sub-microtube heater electrode with outer/inner diameter of 260/100nm, which was fabricated with standard 0.184-μm technology, is proposed for the first time to achieve a reset current of about 0.5 mA. The reasons may be that sub-microtube increases the number of electrode edge and thermal efficiency is improved greatly because the thermal density on the edge of sub-microtube electrode is generally the highest.展开更多
文摘In order to minimize the self-heating effect of the classic SOI devices,SOI structures with Si3 N4 film as a buried insulator （SOSN） are successfully formed using epitaxial layer transfer technology for the first time. The new SOI structures are investigated with high-resolution cross-sectional transmission electron microscopy and spreading resistance profile. Experiment results show that the buried Si3 N4 layer is amorphous and the new SOI material has good structural and electrical properties. The output current characteristics and temperature distribution are simulated and compared to those of standard SOI MOSFETs. Furthermore, the channel temperature and negative differential resistance are reduced during high-temperature operation, suggesting that SOSN can effectively mitigate the selfheating penalty. The new SOI device has been verified in two-dimensional device simulation and indicated that the new structures can reduce device self-heating and increase drain current of the SOI MOSFET.
文摘A damascene structure of phase change memory （PCM） is fabricated successfully with the chemical mechanical polishing （CMP） method, and the CMP of Ge2Sb2Te5 （GST） and Ti films is investigated. The polished surface of wafer is analysed by scanning electron microscopy （SEM） and an energy dispersive spectrometer （EDS）. The measurements show that the damascene device structure of phase change memory is achieved by the CMP process. After the top electrode is deposited, dc sweeping test on PCM reveals that the phase change can be observed. The threshold current of array cells varies between 0.90mA and 1.15mA.
文摘In order to reduce the reset current of cllalcogenide random access memory; a W sub-microtube heater electrode with outer/inner diameter of 260/100nm, which was fabricated with standard 0.184-μm technology, is proposed for the first time to achieve a reset current of about 0.5 mA. The reasons may be that sub-microtube increases the number of electrode edge and thermal efficiency is improved greatly because the thermal density on the edge of sub-microtube electrode is generally the highest.
