This paper presents a 10-bit 20 MS/s pipelined Analog-to- Digital Converter（ADC） using op amp sharing approach and removing Sample and Hold Amplifier（SHA） or SHA-less technique to reach the goal of low-power const...This paper presents a 10-bit 20 MS/s pipelined Analog-to- Digital Converter（ADC） using op amp sharing approach and removing Sample and Hold Amplifier（SHA） or SHA-less technique to reach the goal of low-power constanpfion. This design was fabricated in TSMC 0.18 wn 1P6M technology. Measurement results show at supply voltage of 1.8 V, a SFDR of 42.46 dB, a SNDR of 39.45 dB, an ENOB of 6.26, and a THDof41.82 dB are at 1 MHz sinusoidal sig- nal input. In addition, the DNL and INL are 1.4 LSB and 3.23 LSB respectively. The power onstmaption is 28.8 mW. The core area is 0.595 mm2 and the chip area including pads is 1.468 mm2.展开更多
基金provided by National Chip Implementation Center(CIC)
文摘This paper presents a 10-bit 20 MS/s pipelined Analog-to- Digital Converter（ADC） using op amp sharing approach and removing Sample and Hold Amplifier（SHA） or SHA-less technique to reach the goal of low-power constanpfion. This design was fabricated in TSMC 0.18 wn 1P6M technology. Measurement results show at supply voltage of 1.8 V, a SFDR of 42.46 dB, a SNDR of 39.45 dB, an ENOB of 6.26, and a THDof41.82 dB are at 1 MHz sinusoidal sig- nal input. In addition, the DNL and INL are 1.4 LSB and 3.23 LSB respectively. The power onstmaption is 28.8 mW. The core area is 0.595 mm2 and the chip area including pads is 1.468 mm2.
