The effect of nitric oxide（NO） annealing on charge traps in the oxide insulator and transition layer in n-type4H–Si C metal–oxide–semiconductor（MOS） devices has been investigated using the time-dependent bias s...The effect of nitric oxide（NO） annealing on charge traps in the oxide insulator and transition layer in n-type4H–Si C metal–oxide–semiconductor（MOS） devices has been investigated using the time-dependent bias stress（TDBS）,capacitance–voltage（C–V）,and secondary ion mass spectroscopy（SIMS）.It is revealed that two main categories of charge traps,near interface oxide traps（Nniot） and oxide traps（Not）,have different responses to the TDBS and C–V characteristics in NO-annealed and Ar-annealed samples.The Nniotare mainly responsible for the hysteresis occurring in the bidirectional C–V characteristics,which are very close to the semiconductor interface and can readily exchange charges with the inner semiconductor.However,Not is mainly responsible for the TDBS induced C–V shifts.Electrons tunneling into the Not are hardly released quickly when suffering TDBS,resulting in the problem of the threshold voltage stability.Compared with the Ar-annealed sample,Nniotcan be significantly suppressed by the NO annealing,but there is little improvement of Not.SIMS results demonstrate that the Nniotare distributed within the transition layer,which correlated with the existence of the excess silicon.During the NO annealing process,the excess Si atoms incorporate into nitrogen in the transition layer,allowing better relaxation of the interface strain and effectively reducing the width of the transition layer and the density of Nniot.展开更多
Near-interface oxide traps （NIOTs） in 4H-SiC metal-oxide-semiconductor （MOS） structures fabricated with and without annealing in NO are systematically investigated in this paper. The properties of NIOTs in SiC MOS...Near-interface oxide traps （NIOTs） in 4H-SiC metal-oxide-semiconductor （MOS） structures fabricated with and without annealing in NO are systematically investigated in this paper. The properties of NIOTs in SiC MOS structures prepared with and without annealing in NO are studied and compared in detail. Two main categories of the NIOTs, the “slow” and “fast” NIOTs, are revealed and extracted. The densities of the “fast” NIOTs are determined to be 0.761011 cm-2 and 0.471011 cm-2 for the N2 post oxidation annealing （POA） sample and NO POA sample, respectively. The densities of “slow” NIOTs are 0.791011 cm-2 and 9.441011 cm-2 for the NO POA sample and N2 POA sample, respectively. It is found that the NO POA process only can significantly reduce “slow” NIOTs. However, it has a little effect on “fast” NIOTs. The negative and positive constant voltage stresses （CVS） reveal that electrons captured by those “slow” NIOTs and bulk oxide traps （BOTs） are hardly emitted by the constant voltage stress.展开更多
We investigate the effects of NO annealing and forming gas （FG） annealing on the electrical properties of a SiO2/SiC interface by low-temperature conductance measurements. With nitrogen passivation, the density of i...We investigate the effects of NO annealing and forming gas （FG） annealing on the electrical properties of a SiO2/SiC interface by low-temperature conductance measurements. With nitrogen passivation, the density of interface states （DIT） is significantly reduced in the entire energy range, and the shift of flatband voltage, AVFB, is effectively suppressed to less than 0.4 V. However, very fast states are observed after NO annealing and the response frequencies are higher than 1 MHz at room temperature. After additional FG annealing, the DIT and AVFB are further reduced. The values of the DIT decrease to less than 1011 cm-2 eV- 1 for the energy range of Ec - ET 〉/0.4 eV. It is suggested that the fast states in shallow energy levels originated from the N atoms accumulating at the interface by NO annealing. Though FG annealing has a limited effect on these shallow traps, hydrogen can terminate the residual Si and C dangling bonds corresponding to traps at deep energy levels and improve the interface quality further. It is indicated that NO annealing in conjunction with FG annealing will be a better post-oxidation process method for high performance SiC MOSFETs.展开更多
The interface properties of 4H-SiC metal oxide semiconductor （MOS） capacitors with post-oxidation annealing （POA） in nitric oxide （NO） ambient after high temperature （1300 ℃） oxidation have been investigated ...The interface properties of 4H-SiC metal oxide semiconductor （MOS） capacitors with post-oxidation annealing （POA） in nitric oxide （NO） ambient after high temperature （1300 ℃） oxidation have been investigated using capacitance-voltage （C V） measurements. The experimental results show that the interface states density （Dit） can be obviously decreased by the POA in NO ambient （NO-POA） and further reduced with increasing POA temperature and time. In the meantime significant reduction of the interface states density and oxidation time can be achieved at the higher thermal oxidation temperature, which results in the better oxide MOS characteristics and lower production costs. The dependence of Dit on POA temperature and time has been also discussed in detail.展开更多
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61404098 and 61274079)the Doctoral Fund of Ministry of Education of China(Grant No.20130203120017)+2 种基金the National Key Basic Research Program of China(Grant No.2015CB759600)the National Grid Science&Technology Project,China(Grant No.SGRI-WD-71-14-018)the Key Specific Project in the National Science&Technology Program,China(Grant Nos.2013ZX02305002-002 and 2015CB759600)
文摘The effect of nitric oxide（NO） annealing on charge traps in the oxide insulator and transition layer in n-type4H–Si C metal–oxide–semiconductor（MOS） devices has been investigated using the time-dependent bias stress（TDBS）,capacitance–voltage（C–V）,and secondary ion mass spectroscopy（SIMS）.It is revealed that two main categories of charge traps,near interface oxide traps（Nniot） and oxide traps（Not）,have different responses to the TDBS and C–V characteristics in NO-annealed and Ar-annealed samples.The Nniotare mainly responsible for the hysteresis occurring in the bidirectional C–V characteristics,which are very close to the semiconductor interface and can readily exchange charges with the inner semiconductor.However,Not is mainly responsible for the TDBS induced C–V shifts.Electrons tunneling into the Not are hardly released quickly when suffering TDBS,resulting in the problem of the threshold voltage stability.Compared with the Ar-annealed sample,Nniotcan be significantly suppressed by the NO annealing,but there is little improvement of Not.SIMS results demonstrate that the Nniotare distributed within the transition layer,which correlated with the existence of the excess silicon.During the NO annealing process,the excess Si atoms incorporate into nitrogen in the transition layer,allowing better relaxation of the interface strain and effectively reducing the width of the transition layer and the density of Nniot.
基金Project supported by the National Key Basic Research Program of China(Grant No.2015CB759600)the Natural Science Basic Research Plan in Shaanxi Province,China(Grant No.2017JM6003)the National Natural Science Foundation of China(Grant Nos.61774117 61404098 and 61274079)
文摘Near-interface oxide traps （NIOTs） in 4H-SiC metal-oxide-semiconductor （MOS） structures fabricated with and without annealing in NO are systematically investigated in this paper. The properties of NIOTs in SiC MOS structures prepared with and without annealing in NO are studied and compared in detail. Two main categories of the NIOTs, the “slow” and “fast” NIOTs, are revealed and extracted. The densities of the “fast” NIOTs are determined to be 0.761011 cm-2 and 0.471011 cm-2 for the N2 post oxidation annealing （POA） sample and NO POA sample, respectively. The densities of “slow” NIOTs are 0.791011 cm-2 and 9.441011 cm-2 for the NO POA sample and N2 POA sample, respectively. It is found that the NO POA process only can significantly reduce “slow” NIOTs. However, it has a little effect on “fast” NIOTs. The negative and positive constant voltage stresses （CVS） reveal that electrons captured by those “slow” NIOTs and bulk oxide traps （BOTs） are hardly emitted by the constant voltage stress.
基金supported by the National Natural Science Foundation of China(Nos.61106080,61275042)the National Science and Technology Major Project of the Ministry of Science and Technology of China(No.2013ZX02305)
文摘We investigate the effects of NO annealing and forming gas （FG） annealing on the electrical properties of a SiO2/SiC interface by low-temperature conductance measurements. With nitrogen passivation, the density of interface states （DIT） is significantly reduced in the entire energy range, and the shift of flatband voltage, AVFB, is effectively suppressed to less than 0.4 V. However, very fast states are observed after NO annealing and the response frequencies are higher than 1 MHz at room temperature. After additional FG annealing, the DIT and AVFB are further reduced. The values of the DIT decrease to less than 1011 cm-2 eV- 1 for the energy range of Ec - ET 〉/0.4 eV. It is suggested that the fast states in shallow energy levels originated from the N atoms accumulating at the interface by NO annealing. Though FG annealing has a limited effect on these shallow traps, hydrogen can terminate the residual Si and C dangling bonds corresponding to traps at deep energy levels and improve the interface quality further. It is indicated that NO annealing in conjunction with FG annealing will be a better post-oxidation process method for high performance SiC MOSFETs.
基金Project supported by the National Natural Science Foundation of China(No.61234006)the State Grid of China(No.sgri-wd-71-14-003)
文摘The interface properties of 4H-SiC metal oxide semiconductor （MOS） capacitors with post-oxidation annealing （POA） in nitric oxide （NO） ambient after high temperature （1300 ℃） oxidation have been investigated using capacitance-voltage （C V） measurements. The experimental results show that the interface states density （Dit） can be obviously decreased by the POA in NO ambient （NO-POA） and further reduced with increasing POA temperature and time. In the meantime significant reduction of the interface states density and oxidation time can be achieved at the higher thermal oxidation temperature, which results in the better oxide MOS characteristics and lower production costs. The dependence of Dit on POA temperature and time has been also discussed in detail.
