研究了不同沟道和栅氧化层厚度的n-M O S器件在衬底正偏压的VG=VD/2热载流子应力下,由于衬底正偏压的不同对器件线性漏电流退化的影响。实验发现衬底正偏压对沟长0.135μm,栅氧化层厚度2.5 nm器件的线性漏电流退化的影响比沟长0.25μm,...研究了不同沟道和栅氧化层厚度的n-M O S器件在衬底正偏压的VG=VD/2热载流子应力下,由于衬底正偏压的不同对器件线性漏电流退化的影响。实验发现衬底正偏压对沟长0.135μm,栅氧化层厚度2.5 nm器件的线性漏电流退化的影响比沟长0.25μm,栅氧化层厚度5 nm器件更强。分析结果表明,随着器件沟长继续缩短和栅氧化层减薄,由于衬底正偏置导致的阈值电压减小、增强的寄生NPN晶体管效应、沟道热电子与碰撞电离空穴复合所产生的高能光子以及热电子直接隧穿超薄栅氧化层产生的高能光子可能打断S i-S iO2界面的弱键产生界面陷阱,加速n-M O S器件线性漏电流的退化。展开更多
The effect of HALO dose on device parameter degradation of pMOSFET with 2.1nm o xide and 0.135μm channel length at hot carrier stress is analyzed.It is found that the degradation mechanism is not sensitive to HALO d...The effect of HALO dose on device parameter degradation of pMOSFET with 2.1nm o xide and 0.135μm channel length at hot carrier stress is analyzed.It is found that the degradation mechanism is not sensitive to HALO dose changing,but the d egradation quantities of linear drain current,saturation drain current,and maxim um transconductance increase with HALO dose enhancing and are larger than those of speculated before.The degradation of device parameters (linear drain current, saturation drain current,and maximum transconductance) is attributed to not onl y the drain series resistance enhancing induced by interface states under spacer oxide and carrier mobility degradation but also the threshold voltage variation and initial threshold voltage increasing with HALO dose enhancing.展开更多
Gate current for pMOSFETs is composed of direct tunneling current,channel hot hole,electron injection current,and highly energetic hot holes by secondary impact ionization.The device degradation under V g=V d/2 is m...Gate current for pMOSFETs is composed of direct tunneling current,channel hot hole,electron injection current,and highly energetic hot holes by secondary impact ionization.The device degradation under V g=V d/2 is mainly caused by the injection of hot electrons by primary impact ionization and hot holes by secondary impact ionization,and the device lifetime is assumed to be inversely proportional to the hot holes,which is able to surmount Si-SiO 2 barrier and be injected into the gate oxide.A new lifetime prediction model is proposed on the basis and validated to agree well with the experiment.展开更多
The degradation characteristics of both wide and narrow devices under V _g= V _d/2 stress mode is investigated.The width-enhanced device degradation can be seen with devices narrowing.The main degradation mechanism is...The degradation characteristics of both wide and narrow devices under V _g= V _d/2 stress mode is investigated.The width-enhanced device degradation can be seen with devices narrowing.The main degradation mechanism is interface state generation for pMOSFETs with different channel width.The cause of the width-enhanced device degradation is attributed to the combination of width-enhanced threshold voltage and series resistance.展开更多
文摘研究了不同沟道和栅氧化层厚度的n-M O S器件在衬底正偏压的VG=VD/2热载流子应力下,由于衬底正偏压的不同对器件线性漏电流退化的影响。实验发现衬底正偏压对沟长0.135μm,栅氧化层厚度2.5 nm器件的线性漏电流退化的影响比沟长0.25μm,栅氧化层厚度5 nm器件更强。分析结果表明,随着器件沟长继续缩短和栅氧化层减薄,由于衬底正偏置导致的阈值电压减小、增强的寄生NPN晶体管效应、沟道热电子与碰撞电离空穴复合所产生的高能光子以及热电子直接隧穿超薄栅氧化层产生的高能光子可能打断S i-S iO2界面的弱键产生界面陷阱,加速n-M O S器件线性漏电流的退化。
文摘The effect of HALO dose on device parameter degradation of pMOSFET with 2.1nm o xide and 0.135μm channel length at hot carrier stress is analyzed.It is found that the degradation mechanism is not sensitive to HALO dose changing,but the d egradation quantities of linear drain current,saturation drain current,and maxim um transconductance increase with HALO dose enhancing and are larger than those of speculated before.The degradation of device parameters (linear drain current, saturation drain current,and maximum transconductance) is attributed to not onl y the drain series resistance enhancing induced by interface states under spacer oxide and carrier mobility degradation but also the threshold voltage variation and initial threshold voltage increasing with HALO dose enhancing.
基金国家重点基础研究发展计划 ( No.G2 0 0 0 0 3 65 0 3 ) Motorola Digital DNA Laboratory资助项目~~
文摘Gate current for pMOSFETs is composed of direct tunneling current,channel hot hole,electron injection current,and highly energetic hot holes by secondary impact ionization.The device degradation under V g=V d/2 is mainly caused by the injection of hot electrons by primary impact ionization and hot holes by secondary impact ionization,and the device lifetime is assumed to be inversely proportional to the hot holes,which is able to surmount Si-SiO 2 barrier and be injected into the gate oxide.A new lifetime prediction model is proposed on the basis and validated to agree well with the experiment.
文摘The degradation characteristics of both wide and narrow devices under V _g= V _d/2 stress mode is investigated.The width-enhanced device degradation can be seen with devices narrowing.The main degradation mechanism is interface state generation for pMOSFETs with different channel width.The cause of the width-enhanced device degradation is attributed to the combination of width-enhanced threshold voltage and series resistance.
