Using state assignment to minimize power dissipation and area for finite state ma-chines is computationally hard. Most of published results show that the reduction of switchingactivity often trades with area penalty. ...Using state assignment to minimize power dissipation and area for finite state ma-chines is computationally hard. Most of published results show that the reduction of switchingactivity often trades with area penalty. In this paper, a new approach is proposed. Experimentalresults show a significant reduction of switching activity without area penalty compared withprevious publications.展开更多
For an n-variable Boolean function, there are 2n fixed polarity Reed-Muller(FPRM) forms. In this paper, a frame of power dissipation estimation for FPRM functions ispresented and the polarity conversion is introduced ...For an n-variable Boolean function, there are 2n fixed polarity Reed-Muller(FPRM) forms. In this paper, a frame of power dissipation estimation for FPRM functions ispresented and the polarity conversion is introduced to minimize the power for FPRM functions.Based on searching the best polarity for low power dissipation, an optimal algorithm is proposedand implemented in C. The algorithm is tested on seven single output functions from MCNCbenchmark circuits. The experimental results are shown in this paper.展开更多
A new CMOS quaternary D flip-flop is implemented employing a multiple-valuedclock. PSpice simulation shows that the proposed flip-flop has correct operation. Compared withtraditional multiple-valued flip-flops, the pr...A new CMOS quaternary D flip-flop is implemented employing a multiple-valuedclock. PSpice simulation shows that the proposed flip-flop has correct operation. Compared withtraditional multiple-valued flip-flops, the proposed multiple-valued CMOS flip-flop is characterizedby improved storage capacity, flexible logic structure and reduced power dissipation.展开更多
基金Supported by NNSF of China(Key International Cooperative Project No.60010121219)
文摘Using state assignment to minimize power dissipation and area for finite state ma-chines is computationally hard. Most of published results show that the reduction of switchingactivity often trades with area penalty. In this paper, a new approach is proposed. Experimentalresults show a significant reduction of switching activity without area penalty compared withprevious publications.
文摘For an n-variable Boolean function, there are 2n fixed polarity Reed-Muller(FPRM) forms. In this paper, a frame of power dissipation estimation for FPRM functions ispresented and the polarity conversion is introduced to minimize the power for FPRM functions.Based on searching the best polarity for low power dissipation, an optimal algorithm is proposedand implemented in C. The algorithm is tested on seven single output functions from MCNCbenchmark circuits. The experimental results are shown in this paper.
文摘A new CMOS quaternary D flip-flop is implemented employing a multiple-valuedclock. PSpice simulation shows that the proposed flip-flop has correct operation. Compared withtraditional multiple-valued flip-flops, the proposed multiple-valued CMOS flip-flop is characterizedby improved storage capacity, flexible logic structure and reduced power dissipation.
