A 60 GHz phased array system for mm wave frequency in 5G is introduced and a 5 bit digitally controlled phase shifter in 40 nm CMOS technology is presented.In a phased array system,the signal to noise ratio(SNR)of the...A 60 GHz phased array system for mm wave frequency in 5G is introduced and a 5 bit digitally controlled phase shifter in 40 nm CMOS technology is presented.In a phased array system,the signal to noise ratio(SNR)of the receiver is improved with the beaming forming function.Therefore,the communication data rate and distance are improved accordingly.The phase shifter is the key component for achieving the beam forming function,and its resolution and power consumption are also very critical.In the second half of this paper,an analysis of phase shifter is introduced,and a 60 GHz 5 bit digitally controlled phase shifter in 40 nm complementary metal oxide semiconductor(CMOS)technology is presented.In this presented phase shifter,a hybrid structure is implemented for its advantage on lower phase deviation while keeping comparable loss.Meanwhile,this digitally controlled phase shifter is much more compact than other works.For all 32 states,the minimum phase error is 1.5°,and the maximum phase error is 6.8°.The measured insertion loss is-20.9±1 dB including pad loss at 60 GHz and the return loss is more than 10 dB over 57-64 GHz.The total chip size is 0.24 mm^2 with 0 mW DC power consumption.展开更多
基金supported by the National Science Foundation of China (No. 61828401)
文摘A 60 GHz phased array system for mm wave frequency in 5G is introduced and a 5 bit digitally controlled phase shifter in 40 nm CMOS technology is presented.In a phased array system,the signal to noise ratio(SNR)of the receiver is improved with the beaming forming function.Therefore,the communication data rate and distance are improved accordingly.The phase shifter is the key component for achieving the beam forming function,and its resolution and power consumption are also very critical.In the second half of this paper,an analysis of phase shifter is introduced,and a 60 GHz 5 bit digitally controlled phase shifter in 40 nm complementary metal oxide semiconductor(CMOS)technology is presented.In this presented phase shifter,a hybrid structure is implemented for its advantage on lower phase deviation while keeping comparable loss.Meanwhile,this digitally controlled phase shifter is much more compact than other works.For all 32 states,the minimum phase error is 1.5°,and the maximum phase error is 6.8°.The measured insertion loss is-20.9±1 dB including pad loss at 60 GHz and the return loss is more than 10 dB over 57-64 GHz.The total chip size is 0.24 mm^2 with 0 mW DC power consumption.
