本文构建了一种新型的分子印迹电化学发光(MIP-ECL)生物传感器,可高灵敏、高选择性测定普萘洛尔(PRO)分子。钌硅纳米粒子(Ru Si NPs)与聚乙烯亚胺(PEI)通过静电吸附形成Ru Si@PEI复合纳米粒子,这种纳米复合结构缩短了电子转移距离,进而...本文构建了一种新型的分子印迹电化学发光(MIP-ECL)生物传感器,可高灵敏、高选择性测定普萘洛尔(PRO)分子。钌硅纳米粒子(Ru Si NPs)与聚乙烯亚胺(PEI)通过静电吸附形成Ru Si@PEI复合纳米粒子,这种纳米复合结构缩短了电子转移距离,进而提高了电子转移效率,有效增强ECL信号。利用透射电镜(TEM)、扫描电镜(SEM)、紫外-可见(UV-Vis)光谱和ECL等方法对合成Ru Si@PEI纳米粒子进行表征。以该复合纳米材料作为ECL探针,在此基础上与PRO印迹的聚合物膜结合,构建MIP-ECL传感器。实验对Ru Si@PEI纳米粒子合成过程中Ru Si NPs与PEI的体积比,洗脱与孵育时间进行优化,在最优条件下记录PRO被洗脱与重新印迹到传感器上时ECL信号的差值,其差值与PRO浓度之间呈现良好的线性关系,检测范围为1.0×10^(-11)~5.0×10^(-9)mol/L,检测限(S/N=3)低至5.4×10^(-13)mol/L。此外传感器在人血清样品中加标回收率为93.8%~112.7%,说明了该MIP-ECL传感器在复杂生物样品的PRO检测中具有潜在应用价值。展开更多
A novel Parallel-Based Lifting Algorithm （PBLA） for Discrete Wavelet Transform （DWT）, exploiting the parallelism of arithmetic operations in all lifting steps, is proposed in this paper. It leads to reduce the cri...A novel Parallel-Based Lifting Algorithm （PBLA） for Discrete Wavelet Transform （DWT）, exploiting the parallelism of arithmetic operations in all lifting steps, is proposed in this paper. It leads to reduce the critical path latency of computation, and to reduce the complexity of hardware implementation as well. The detailed derivation on the proposed algorithm, as well as the resulting Very Large Scale Integration （VLSI） architecture, is introduced, taking the 9/7 DWT as an example but without loss of generality. In comparison with the Conventional Lifting Algorithm Based Implementation （CLABI）, the critical path latency of the proposed architecture is reduced by more than half from （4Tm ＋ 8Ta）to Tm ＋ 4Ta, and is competitive to that of Convolution-Based Implementation （CBI）, but the new implementation will save significantly in hardware. The experimental results demonstrate that the proposed architecture has good performance in both increasing working frequency and reducing area.展开更多
This paper presents a robust face recognition algorithm by using transform domain-based multiple feature fusion and lin- ear regression. Transform domain-based feature fusion can provide comprehensive face information...This paper presents a robust face recognition algorithm by using transform domain-based multiple feature fusion and lin- ear regression. Transform domain-based feature fusion can provide comprehensive face information for recognition, and decrease the effect of variations in illumination and pose. The holistic feature and local feature are extracted by discrete cosine transform and Gabor wavelet transform, respectively. Then the extracted holistic features and the local features are fused by weighted sum. The fused feature values are finally sent to linear regression classifier for recognition. The algorithm is evaluated on AR, ORL and Yale B face databases. Experiment results show that our proposed algo- rithm could be more robust than those single feature-based algo- rithms under pose and expression variations.展开更多
This paper introduced a novel high performance algorithm and VLSI architectures for achieving bit plane coding （BPC） in word level sequential and parallel mode. The proposed BPC algorithm adopts the techniques of co...This paper introduced a novel high performance algorithm and VLSI architectures for achieving bit plane coding （BPC） in word level sequential and parallel mode. The proposed BPC algorithm adopts the techniques of coding pass prediction and parallel ＆ pipeline to reduce the number of accessing memory and to increase the ability of concurrently processing of the system, where all the coefficient bits of a code block could be coded by only one scan. A new parallel bit plane architecture （PA） was proposed to achieve word-level sequential coding. Moreover, an efficient high-speed architecture （HA） was presented to achieve multi-word parallel coding. Compared to the state of the art, the proposed PA could reduce the hardware cost more efficiently, though the throughput retains one coefficient coded per clock. While the proposed HA could perform coding for 4 coefficients belonging to a stripe column at one intra-clock cycle, so that coding for an NxN code-block could be completed in approximate N2/4 intra-clock cycles. Theoretical analysis and experimental results demonstrate that the proposed designs have high throughput rate with good performance in terms of speedup to cost, which can be good alternatives for low power applications.展开更多
文摘本文构建了一种新型的分子印迹电化学发光(MIP-ECL)生物传感器,可高灵敏、高选择性测定普萘洛尔(PRO)分子。钌硅纳米粒子(Ru Si NPs)与聚乙烯亚胺(PEI)通过静电吸附形成Ru Si@PEI复合纳米粒子,这种纳米复合结构缩短了电子转移距离,进而提高了电子转移效率,有效增强ECL信号。利用透射电镜(TEM)、扫描电镜(SEM)、紫外-可见(UV-Vis)光谱和ECL等方法对合成Ru Si@PEI纳米粒子进行表征。以该复合纳米材料作为ECL探针,在此基础上与PRO印迹的聚合物膜结合,构建MIP-ECL传感器。实验对Ru Si@PEI纳米粒子合成过程中Ru Si NPs与PEI的体积比,洗脱与孵育时间进行优化,在最优条件下记录PRO被洗脱与重新印迹到传感器上时ECL信号的差值,其差值与PRO浓度之间呈现良好的线性关系,检测范围为1.0×10^(-11)~5.0×10^(-9)mol/L,检测限(S/N=3)低至5.4×10^(-13)mol/L。此外传感器在人血清样品中加标回收率为93.8%~112.7%,说明了该MIP-ECL传感器在复杂生物样品的PRO检测中具有潜在应用价值。
基金Supported by the National 863 project (No.2002AA133010).
文摘A novel Parallel-Based Lifting Algorithm （PBLA） for Discrete Wavelet Transform （DWT）, exploiting the parallelism of arithmetic operations in all lifting steps, is proposed in this paper. It leads to reduce the critical path latency of computation, and to reduce the complexity of hardware implementation as well. The detailed derivation on the proposed algorithm, as well as the resulting Very Large Scale Integration （VLSI） architecture, is introduced, taking the 9/7 DWT as an example but without loss of generality. In comparison with the Conventional Lifting Algorithm Based Implementation （CLABI）, the critical path latency of the proposed architecture is reduced by more than half from （4Tm ＋ 8Ta）to Tm ＋ 4Ta, and is competitive to that of Convolution-Based Implementation （CBI）, but the new implementation will save significantly in hardware. The experimental results demonstrate that the proposed architecture has good performance in both increasing working frequency and reducing area.
基金Supported by the National Science Foundation of China(60972081)Hubei Natural Science Foundation of China(2013CFC118,2009CDA139)+3 种基金Special Funds for Shenzhen Strategic New Industry Development(JCYJ 20120616135936123)Special Project on the Integration of Industry,Education and Research of Ministry of Education of Guangdong Province(2011B090400477)Special Project on the Integration of Industry,Education and Research of Zhuhai City(2011A050101005,2012D0501990016)Zhuhai Key Laboratory Program for Science and Technique(2012D050 1990026)
文摘This paper presents a robust face recognition algorithm by using transform domain-based multiple feature fusion and lin- ear regression. Transform domain-based feature fusion can provide comprehensive face information for recognition, and decrease the effect of variations in illumination and pose. The holistic feature and local feature are extracted by discrete cosine transform and Gabor wavelet transform, respectively. Then the extracted holistic features and the local features are fused by weighted sum. The fused feature values are finally sent to linear regression classifier for recognition. The algorithm is evaluated on AR, ORL and Yale B face databases. Experiment results show that our proposed algo- rithm could be more robust than those single feature-based algo- rithms under pose and expression variations.
基金the Natural Science Foundation of Hubei Province (Grant No. 2006ABA370)Civil Research Project of State Defense (Grant No. C1120061304)+1 种基金National Natural Science Foundation of China (Grant No. 60572048)National High Technology Research and Develop-ment of China (863 Program) (Grant No. 2004AA119010-6)
文摘This paper introduced a novel high performance algorithm and VLSI architectures for achieving bit plane coding （BPC） in word level sequential and parallel mode. The proposed BPC algorithm adopts the techniques of coding pass prediction and parallel ＆ pipeline to reduce the number of accessing memory and to increase the ability of concurrently processing of the system, where all the coefficient bits of a code block could be coded by only one scan. A new parallel bit plane architecture （PA） was proposed to achieve word-level sequential coding. Moreover, an efficient high-speed architecture （HA） was presented to achieve multi-word parallel coding. Compared to the state of the art, the proposed PA could reduce the hardware cost more efficiently, though the throughput retains one coefficient coded per clock. While the proposed HA could perform coding for 4 coefficients belonging to a stripe column at one intra-clock cycle, so that coding for an NxN code-block could be completed in approximate N2/4 intra-clock cycles. Theoretical analysis and experimental results demonstrate that the proposed designs have high throughput rate with good performance in terms of speedup to cost, which can be good alternatives for low power applications.
