This paper presents an algorithm that combines the chaos optimization algorithm with the maximum entropy ( COA-ME) by using entropy model based on chaos algorithm,in which the maximum entropy is used as the second met...This paper presents an algorithm that combines the chaos optimization algorithm with the maximum entropy ( COA-ME) by using entropy model based on chaos algorithm,in which the maximum entropy is used as the second method of searching the excellent solution. The search direction is improved by chaos optimization algorithm and realizes the selective acceptance of wrong solution. The experimental result shows that the presented algorithm can be used in the partitioning of hardware/software of reconfigurable system. It effectively reduces the local extremum problem,and search speed as well as performance of partitioning is improved.展开更多
With the development of the design complexity in embedded systems, hardware/software （HW/SW） partitioning becomes a challenging optimization problem in HW/SW co-design. A novel HW/SW partitioning method based on pos...With the development of the design complexity in embedded systems, hardware/software （HW/SW） partitioning becomes a challenging optimization problem in HW/SW co-design. A novel HW/SW partitioning method based on position disturbed particle swarm optimization with invasive weed optimization （PDPSO-IWO） is presented in this paper. It is found by biologists that the ground squirrels produce alarm calls which warn their peers to move away when there is potential predatory threat. Here, we present PDPSO algorithm, in each iteration of which the squirrel behavior of escaping from the global worst particle can be simulated to increase population diversity and avoid local optimum. We also present new initialization and reproduction strategies to improve IWO algorithm for searching a better position, with which the global best position can be updated. Then the search accuracy and the solution quality can be enhanced. PDPSO and improved IWO are synthesized into one single PDPSO-IWO algorithm, which can keep both searching diversification and searching intensification. Furthermore, a hybrid NodeRank （HNodeRank） algorithm is proposed to initialize the population of PDPSO-IWO, and the solution quality can be enhanced further. Since the HW/SW communication cost computing is the most time-consuming process for HW/SW partitioning algorithm, we adopt the GPU parallel technique to accelerate the computing. In this way, the runtime of PDPSO-IWO for large-scale HW/SW partitioning problem can be reduced efficiently. Finally, multiple experiments on benchmarks from state-of-the-art publications and large-scale HW/SW partitioning demonstrate that the proposed algorithm can achieve higher performance than other algorithms.展开更多
This paper focuses on the algorithmic aspects for the hardware/software （HW/SW） partitioning which searches a reasonable composition of hardware and software components which not only satisfies the constraint of har...This paper focuses on the algorithmic aspects for the hardware/software （HW/SW） partitioning which searches a reasonable composition of hardware and software components which not only satisfies the constraint of hardware area but also optimizes the execution time. The computational model is extended so that all possible types of communications can be taken into account for the HW/SW partitioning. Also, a new dynamic programming algorithm is proposed on the basis of the computational model, in which source data, rather than speedup in previous work, of basic scheduling blocks are directly utilized to calculate the optimal solution. The proposed algorithm runs in O（n·A） for n code fragments and the available hardware area A. Simulation results show that the proposed algorithm solves the HW/SW partitioning without increase in running time, compared with the algorithm cited in the literature.展开更多
Hardware/software partitioning is an important step in the design of embedded systems. In this paper, the hardware/software partitioning problem is modeled as a constrained binary integer programming problem, which is...Hardware/software partitioning is an important step in the design of embedded systems. In this paper, the hardware/software partitioning problem is modeled as a constrained binary integer programming problem, which is further converted equivalently to an unconstrained binary integer programming problem by a penalty method. A local search method, HSFM, is developed to obtain a discrete local minimizer of the unconstrained binary integer programming problem. Next, an auxiliary function, which has the same global optimal solutions as the unconstrained binary integer programming problem, is constructed, and its properties are studied. We show that applying HSFM to minimize the auxiliary function can escape from previous local optima by the increase of the parameter value successfully. Finally, a discrete dynamic convexized method is developed to solve the hardware/software partitioning problem. Computational results and comparisons indicate that the proposed algorithm can get high-quality solutions.展开更多
A hardware/software co-synthesis method is presented for SoC designs consisting of both hardware IP cores and software components on a graph-theoretic formulation. Given a SoC integrated with a set of functions and a ...A hardware/software co-synthesis method is presented for SoC designs consisting of both hardware IP cores and software components on a graph-theoretic formulation. Given a SoC integrated with a set of functions and a set of performance factors, a core for each function is selected from a set of alternative IP cores and software components, and optimal partitions is found in a way to evenly balance the performance factors and to ultimately reduce the overall cost, size, power consumption and runtime of the core-based SoC. The algorithm formulates IP cores and components into the corresponding mathematical models, presents a graph-theoretic model for finding the optimal partitions of SoC design and transforms SoC hardware/software co-synthesis problem into finding optimal paths in a weighted, directed graph. Overcoming the three main deficiencies of the traditional methods, this method can work automatically, evaluate more performance factors at the same time and meet the particularity of SoC designs. At last, the approach is illustrated that is practical and effective through partitioning a practical system.展开更多
Ethernet over SDH/SONET (EOS) is a hotspot in today's data transmission technology for it combines the merits of both Ethernet and SDH/SONET. However, implementing an EOS system on a chip is complex and needs full...Ethernet over SDH/SONET (EOS) is a hotspot in today's data transmission technology for it combines the merits of both Ethernet and SDH/SONET. However, implementing an EOS system on a chip is complex and needs full verifications. This paper introduces our design of Hardware/Software co-verification platform for EOS design. The hardware platform contains a microprocessor board and an FPGA (Field Programmable Gate Array)-based verification board, and the corresponding software includes test benches running in FPGAs, controlling programs for the microprocessor and a console program with GUI (Graphical User Interface) interface for configuration, management and supervision. The design is cost-effective and has been successfully employed to verify several IP (Intellectual Property) blocks of our EOS chip. Moreover, it is flexible and can be applied as a general-purpose verification platform.展开更多
In this paper, the storage capacity of communication among cores and processors is taken into account and a maximum D-value-first algorithm is proposed. By improving the hardware parallelism in the task execution proc...In this paper, the storage capacity of communication among cores and processors is taken into account and a maximum D-value-first algorithm is proposed. By improving the hardware parallelism in the task execution process, the maximum storage requirements for communication are minimized. Experimental results with various directed acyclic graph models showed that compared with the earliest-task-first algorithm, the storage requirements for communication were reduced by 22.46%, on average, while the average of makespan only increased by 0.82%,.展开更多
In order to improve the efficiency of embedded software running on processor core, this paper proposes a hard-ware/software co-optimization approach for embedded software from the system point of view. The proposed st...In order to improve the efficiency of embedded software running on processor core, this paper proposes a hard-ware/software co-optimization approach for embedded software from the system point of view. The proposed stepwise methods aim at exploiting the structure and the resources of the processor as much as possible for software algorithm optimization. To achieve low memory usage and low frequency need for the same performance, this co-optimization approach was used to optimize embedded software of MP3 decoder based on a 16-bit fixed-point DSP core. After the optimization, the results of decoding 128 kbps, 44.1 kHz stereo MP3 on DSP evaluation platform need 45.9 MIPS and 20.4 kbytes memory space. The optimization rate achieves 65.6% for memory and 49.6% for frequency respectively compared with the results by compiler using floating-point computation. The experimental result indicates the availability of the hardware/software co-optimization approach depending on the algorithm and architecture.展开更多
This paper deals with a new hardware/software embedded system design methodology based on design pattern approach by development of a new design tool called smartcell. Three main constraints of embedded systems design...This paper deals with a new hardware/software embedded system design methodology based on design pattern approach by development of a new design tool called smartcell. Three main constraints of embedded systems design process are investigated: the complexity, the partitioning between hardware and software aspects and the reusability. Two intermediate models are carried out in order to solve the complexity problem. The partitioning problem deals with the proposed hardware/software partitioning algorithm based on Ant Colony Optimisation. The reusability problem is resolved by synthesis of intellectual property blocks. Specification and integration of an intelligent controller on heterogeneous platform are considered to illustrate the proposed approach.展开更多
We present a simulation framework for wireless sensor networks developed to allow the design exploration and the complete microprocessor-instruction-level debug of network formation, data congestion, nodes interaction...We present a simulation framework for wireless sensor networks developed to allow the design exploration and the complete microprocessor-instruction-level debug of network formation, data congestion, nodes interaction, all in one simulation environment. A specifically innovative feature is the co-emulation of selected nodes at clock-cycle-accurate hardware processing level, allowing code debug and exact execution latency evaluation (considering both protocol stack and application), together with other nodes at abstract protocol level, meeting a designer’s needs of simulation speed, scalability and reliability. The simulator is centered on the Zigbee protocol and can be retargeted for different node micro-architectures.展开更多
Graph processing has been widely used in many scenarios,from scientific computing to artificial intelligence.Graph processing exhibits irregular computational parallelism and random memory accesses,unlike traditional ...Graph processing has been widely used in many scenarios,from scientific computing to artificial intelligence.Graph processing exhibits irregular computational parallelism and random memory accesses,unlike traditional workloads.Therefore,running graph processing workloads on conventional architectures(e.g.,CPUs and GPUs)often shows a significantly low compute-memory ratio with few performance benefits,which can be,in many cases,even slower than a specialized single-thread graph algorithm.While domain-specific hardware designs are essential for graph processing,it is still challenging to transform the hardware capability to performance boost without coupled software codesigns.This article presents a graph processing ecosystem from hardware to software.We start by introducing a series of hardware accelerators as the foundation of this ecosystem.Subsequently,the codesigned parallel graph systems and their distributed techniques are presented to support graph applications.Finally,we introduce our efforts on novel graph applications and hardware architectures.Extensive results show that various graph applications can be efficiently accelerated in this graph processing ecosystem.展开更多
The functions and characteristics of software radio are discussed. Using techniques and method of software radio, the concept and advantages of a new kind of radio fuze, software radio fuze, are analysed. Several kind...The functions and characteristics of software radio are discussed. Using techniques and method of software radio, the concept and advantages of a new kind of radio fuze, software radio fuze, are analysed. Several kinds of hardware platform structures of the software radio fuze are studied and the key techniques are analysed. The software radio fuze will become the most promising radio fuze techniques in 21st century.展开更多
With the introduction of software defined hardware by DARPA Electronics Resurgence Initiative,software definition will be the basic attribute of information system.Benefiting from boundary certainty and algorithm aggr...With the introduction of software defined hardware by DARPA Electronics Resurgence Initiative,software definition will be the basic attribute of information system.Benefiting from boundary certainty and algorithm aggregation of domain applications,domain-oriented computing architecture has become the technical direction that considers the high flexibility and efficiency of information system.Aiming at the characteristics of data-intensive computing in different scenarios such as Internet of Things(IoT),big data,artificial intelligence(AI),this paper presents a domain-oriented software defined computing architecture,discusses the hierarchical interconnection structure,hybrid granularity computing element and its computational kernel extraction method,finally proves the flexibility and high efficiency of this architecture by experimental comparison.展开更多
Software can be seen almost everywhere and is now defining the world.Software has transitioned from an affiliate of hardware,to a network service that is present in every corner of our social lives.
Nowadays, from home monitoring to large airport security, a lot of digital video surveillance systems have been used. Digital surveillance system usually requires streaming video processing abilities. As an advanced v...Nowadays, from home monitoring to large airport security, a lot of digital video surveillance systems have been used. Digital surveillance system usually requires streaming video processing abilities. As an advanced video coding method, H.264 is introduced to reduce the large video data dramatically (usually by 70X or more). However, computational overhead occurs when coding and decoding H.264 video. In this paper, a System-on-a-Chip (SoC) based hardware acceleration solution for video codec is proposed, which can also be used for other software applications. The characteristics of the video codec are analyzed by using the profiling tool. The Hadamard function, which is the bottleneck of H.264, is identified not only by execution time but also another two attributes, such as cycle per loop and loop round. The Co-processor approach is applied to accelerate the Hadamard function by transforming it to hardware. Performance improvement, resource costs and energy consumption are compared and analyzed. Experimental results indicate that 76.5% energy deduction and 8.09X speedup can be reached after balancing these three key factors.展开更多
New theories,methodologies,and technologies have been continuously invented and widely applied in modern software development,along with many new tools and best practices that are of remarkable significance in the sof...New theories,methodologies,and technologies have been continuously invented and widely applied in modern software development,along with many new tools and best practices that are of remarkable significance in the software industry.In Software Engineering(SE)programs of universities,it is quite difficult for their curricula to chase after the fast-evolving technology trend.As a consequence,there have been significant challenges in designing an evolvable SE curriculum.In this paper,we present a knowledge graph based curriculum design method for SE programs.Knowledge Points(KPs)are organized into a multi-layer and multi-dimensionally annotated knowledge graph called SEKG,and five principles are applied to partition the SEKG into a set of inter-related courses.Metrics for evaluating the quality of an SE curriculum are briefly discussed.This method can not only help design a systematic curriculum from existing software engineering KPs but also facilitate curriculum evolution to adapt to technology trends.展开更多
随着电子计算机的日益普及,今天在美国由—ware这个构词成分所组成的词屡屡可见。据美国哈佛大学的教育学教授 Howard Gardner声称,在近期召开的一次有关人工智能的学术会议之后,—ware词突然变得风靡起来。一位长期从事人类记忆研究的...随着电子计算机的日益普及,今天在美国由—ware这个构词成分所组成的词屡屡可见。据美国哈佛大学的教育学教授 Howard Gardner声称,在近期召开的一次有关人工智能的学术会议之后,—ware词突然变得风靡起来。一位长期从事人类记忆研究的神经生物家甚至说,他觉得自已还不能适应这种情况,完全成了“a student of wetware among thecomputer hackers”(处在电子计算机专家中间一名学生)。从80年代初开始,wetware一词便被用来指 human brain。本来也可以用另外几个词:skullware,grayware(gray展开更多
基金Sponsored by the Natural Science Foundation of Heilongjiang Province( Grant No B2007-07)Industrial Research Projects in Qiqihaer( Grant No GYGG-09009)
文摘This paper presents an algorithm that combines the chaos optimization algorithm with the maximum entropy ( COA-ME) by using entropy model based on chaos algorithm,in which the maximum entropy is used as the second method of searching the excellent solution. The search direction is improved by chaos optimization algorithm and realizes the selective acceptance of wrong solution. The experimental result shows that the presented algorithm can be used in the partitioning of hardware/software of reconfigurable system. It effectively reduces the local extremum problem,and search speed as well as performance of partitioning is improved.
基金The work was supported by the National Natural Science Foundation of China under Grant No. 61472289 and the National Key Research and Development Project of China under Grant No. 2016YFC0106305.
文摘With the development of the design complexity in embedded systems, hardware/software （HW/SW） partitioning becomes a challenging optimization problem in HW/SW co-design. A novel HW/SW partitioning method based on position disturbed particle swarm optimization with invasive weed optimization （PDPSO-IWO） is presented in this paper. It is found by biologists that the ground squirrels produce alarm calls which warn their peers to move away when there is potential predatory threat. Here, we present PDPSO algorithm, in each iteration of which the squirrel behavior of escaping from the global worst particle can be simulated to increase population diversity and avoid local optimum. We also present new initialization and reproduction strategies to improve IWO algorithm for searching a better position, with which the global best position can be updated. Then the search accuracy and the solution quality can be enhanced. PDPSO and improved IWO are synthesized into one single PDPSO-IWO algorithm, which can keep both searching diversification and searching intensification. Furthermore, a hybrid NodeRank （HNodeRank） algorithm is proposed to initialize the population of PDPSO-IWO, and the solution quality can be enhanced further. Since the HW/SW communication cost computing is the most time-consuming process for HW/SW partitioning algorithm, we adopt the GPU parallel technique to accelerate the computing. In this way, the runtime of PDPSO-IWO for large-scale HW/SW partitioning problem can be reduced efficiently. Finally, multiple experiments on benchmarks from state-of-the-art publications and large-scale HW/SW partitioning demonstrate that the proposed algorithm can achieve higher performance than other algorithms.
文摘This paper focuses on the algorithmic aspects for the hardware/software （HW/SW） partitioning which searches a reasonable composition of hardware and software components which not only satisfies the constraint of hardware area but also optimizes the execution time. The computational model is extended so that all possible types of communications can be taken into account for the HW/SW partitioning. Also, a new dynamic programming algorithm is proposed on the basis of the computational model, in which source data, rather than speedup in previous work, of basic scheduling blocks are directly utilized to calculate the optimal solution. The proposed algorithm runs in O（n·A） for n code fragments and the available hardware area A. Simulation results show that the proposed algorithm solves the HW/SW partitioning without increase in running time, compared with the algorithm cited in the literature.
基金Supported by the National Natural Science Foundation of China(11301255)the Fund by Collaborative Innovation Center of IoT Industrialization and Intelligent Production,Minjiang University(IIC1703)+1 种基金Foundation of Minjiang University(MYK17032)the Program for New Century Excellent Talents in Fujian Province University
文摘Hardware/software partitioning is an important step in the design of embedded systems. In this paper, the hardware/software partitioning problem is modeled as a constrained binary integer programming problem, which is further converted equivalently to an unconstrained binary integer programming problem by a penalty method. A local search method, HSFM, is developed to obtain a discrete local minimizer of the unconstrained binary integer programming problem. Next, an auxiliary function, which has the same global optimal solutions as the unconstrained binary integer programming problem, is constructed, and its properties are studied. We show that applying HSFM to minimize the auxiliary function can escape from previous local optima by the increase of the parameter value successfully. Finally, a discrete dynamic convexized method is developed to solve the hardware/software partitioning problem. Computational results and comparisons indicate that the proposed algorithm can get high-quality solutions.
基金This project was supported by the Defense Pre-Research Project of the ‘Tenth Five-Year-Plan’ of China(41315040106) and the National"863"High Technology Research and Development Programof China (2003AAIZ2210)
文摘A hardware/software co-synthesis method is presented for SoC designs consisting of both hardware IP cores and software components on a graph-theoretic formulation. Given a SoC integrated with a set of functions and a set of performance factors, a core for each function is selected from a set of alternative IP cores and software components, and optimal partitions is found in a way to evenly balance the performance factors and to ultimately reduce the overall cost, size, power consumption and runtime of the core-based SoC. The algorithm formulates IP cores and components into the corresponding mathematical models, presents a graph-theoretic model for finding the optimal partitions of SoC design and transforms SoC hardware/software co-synthesis problem into finding optimal paths in a weighted, directed graph. Overcoming the three main deficiencies of the traditional methods, this method can work automatically, evaluate more performance factors at the same time and meet the particularity of SoC designs. At last, the approach is illustrated that is practical and effective through partitioning a practical system.
文摘Ethernet over SDH/SONET (EOS) is a hotspot in today's data transmission technology for it combines the merits of both Ethernet and SDH/SONET. However, implementing an EOS system on a chip is complex and needs full verifications. This paper introduces our design of Hardware/Software co-verification platform for EOS design. The hardware platform contains a microprocessor board and an FPGA (Field Programmable Gate Array)-based verification board, and the corresponding software includes test benches running in FPGAs, controlling programs for the microprocessor and a console program with GUI (Graphical User Interface) interface for configuration, management and supervision. The design is cost-effective and has been successfully employed to verify several IP (Intellectual Property) blocks of our EOS chip. Moreover, it is flexible and can be applied as a general-purpose verification platform.
基金Supported by the National Natural Science Foundation of China(No.61179045 and No.61350009)
文摘In this paper, the storage capacity of communication among cores and processors is taken into account and a maximum D-value-first algorithm is proposed. By improving the hardware parallelism in the task execution process, the maximum storage requirements for communication are minimized. Experimental results with various directed acyclic graph models showed that compared with the earliest-task-first algorithm, the storage requirements for communication were reduced by 22.46%, on average, while the average of makespan only increased by 0.82%,.
基金Project supported by the Key-Tech Program of Zhejiang Province,China (No. 021101559), and the Fok Ying Tong Education Founda-tion (No. 94031), China
文摘In order to improve the efficiency of embedded software running on processor core, this paper proposes a hard-ware/software co-optimization approach for embedded software from the system point of view. The proposed stepwise methods aim at exploiting the structure and the resources of the processor as much as possible for software algorithm optimization. To achieve low memory usage and low frequency need for the same performance, this co-optimization approach was used to optimize embedded software of MP3 decoder based on a 16-bit fixed-point DSP core. After the optimization, the results of decoding 128 kbps, 44.1 kHz stereo MP3 on DSP evaluation platform need 45.9 MIPS and 20.4 kbytes memory space. The optimization rate achieves 65.6% for memory and 49.6% for frequency respectively compared with the results by compiler using floating-point computation. The experimental result indicates the availability of the hardware/software co-optimization approach depending on the algorithm and architecture.
文摘This paper deals with a new hardware/software embedded system design methodology based on design pattern approach by development of a new design tool called smartcell. Three main constraints of embedded systems design process are investigated: the complexity, the partitioning between hardware and software aspects and the reusability. Two intermediate models are carried out in order to solve the complexity problem. The partitioning problem deals with the proposed hardware/software partitioning algorithm based on Ant Colony Optimisation. The reusability problem is resolved by synthesis of intellectual property blocks. Specification and integration of an intelligent controller on heterogeneous platform are considered to illustrate the proposed approach.
文摘We present a simulation framework for wireless sensor networks developed to allow the design exploration and the complete microprocessor-instruction-level debug of network formation, data congestion, nodes interaction, all in one simulation environment. A specifically innovative feature is the co-emulation of selected nodes at clock-cycle-accurate hardware processing level, allowing code debug and exact execution latency evaluation (considering both protocol stack and application), together with other nodes at abstract protocol level, meeting a designer’s needs of simulation speed, scalability and reliability. The simulator is centered on the Zigbee protocol and can be retargeted for different node micro-architectures.
基金supported by the National Key Research and Development Program of China under Grant No.2023YFB4502300.
文摘Graph processing has been widely used in many scenarios,from scientific computing to artificial intelligence.Graph processing exhibits irregular computational parallelism and random memory accesses,unlike traditional workloads.Therefore,running graph processing workloads on conventional architectures(e.g.,CPUs and GPUs)often shows a significantly low compute-memory ratio with few performance benefits,which can be,in many cases,even slower than a specialized single-thread graph algorithm.While domain-specific hardware designs are essential for graph processing,it is still challenging to transform the hardware capability to performance boost without coupled software codesigns.This article presents a graph processing ecosystem from hardware to software.We start by introducing a series of hardware accelerators as the foundation of this ecosystem.Subsequently,the codesigned parallel graph systems and their distributed techniques are presented to support graph applications.Finally,we introduce our efforts on novel graph applications and hardware architectures.Extensive results show that various graph applications can be efficiently accelerated in this graph processing ecosystem.
文摘The functions and characteristics of software radio are discussed. Using techniques and method of software radio, the concept and advantages of a new kind of radio fuze, software radio fuze, are analysed. Several kinds of hardware platform structures of the software radio fuze are studied and the key techniques are analysed. The software radio fuze will become the most promising radio fuze techniques in 21st century.
基金supported by National Science and Technology Major Project granted No.2016ZX01012101
文摘With the introduction of software defined hardware by DARPA Electronics Resurgence Initiative,software definition will be the basic attribute of information system.Benefiting from boundary certainty and algorithm aggregation of domain applications,domain-oriented computing architecture has become the technical direction that considers the high flexibility and efficiency of information system.Aiming at the characteristics of data-intensive computing in different scenarios such as Internet of Things(IoT),big data,artificial intelligence(AI),this paper presents a domain-oriented software defined computing architecture,discusses the hierarchical interconnection structure,hybrid granularity computing element and its computational kernel extraction method,finally proves the flexibility and high efficiency of this architecture by experimental comparison.
文摘Software can be seen almost everywhere and is now defining the world.Software has transitioned from an affiliate of hardware,to a network service that is present in every corner of our social lives.
文摘Nowadays, from home monitoring to large airport security, a lot of digital video surveillance systems have been used. Digital surveillance system usually requires streaming video processing abilities. As an advanced video coding method, H.264 is introduced to reduce the large video data dramatically (usually by 70X or more). However, computational overhead occurs when coding and decoding H.264 video. In this paper, a System-on-a-Chip (SoC) based hardware acceleration solution for video codec is proposed, which can also be used for other software applications. The characteristics of the video codec are analyzed by using the profiling tool. The Hadamard function, which is the bottleneck of H.264, is identified not only by execution time but also another two attributes, such as cycle per loop and loop round. The Co-processor approach is applied to accelerate the Hadamard function by transforming it to hardware. Performance improvement, resource costs and energy consumption are compared and analyzed. Experimental results indicate that 76.5% energy deduction and 8.09X speedup can be reached after balancing these three key factors.
文摘New theories,methodologies,and technologies have been continuously invented and widely applied in modern software development,along with many new tools and best practices that are of remarkable significance in the software industry.In Software Engineering(SE)programs of universities,it is quite difficult for their curricula to chase after the fast-evolving technology trend.As a consequence,there have been significant challenges in designing an evolvable SE curriculum.In this paper,we present a knowledge graph based curriculum design method for SE programs.Knowledge Points(KPs)are organized into a multi-layer and multi-dimensionally annotated knowledge graph called SEKG,and five principles are applied to partition the SEKG into a set of inter-related courses.Metrics for evaluating the quality of an SE curriculum are briefly discussed.This method can not only help design a systematic curriculum from existing software engineering KPs but also facilitate curriculum evolution to adapt to technology trends.
文摘随着电子计算机的日益普及,今天在美国由—ware这个构词成分所组成的词屡屡可见。据美国哈佛大学的教育学教授 Howard Gardner声称,在近期召开的一次有关人工智能的学术会议之后,—ware词突然变得风靡起来。一位长期从事人类记忆研究的神经生物家甚至说,他觉得自已还不能适应这种情况,完全成了“a student of wetware among thecomputer hackers”(处在电子计算机专家中间一名学生)。从80年代初开始,wetware一词便被用来指 human brain。本来也可以用另外几个词:skullware,grayware(gray
