A modified Benes network is proposed to be used as an optimal shuffle network in worldwide interoperability for microwave access （WiMAX） low density parity check （LDPC） decoders, When the size of the input is not ...A modified Benes network is proposed to be used as an optimal shuffle network in worldwide interoperability for microwave access （WiMAX） low density parity check （LDPC） decoders, When the size of the input is not a power of two, the modified Benes network can achieve the most optimal performance. This modified Benes network is non-blocking and can perform any sorts of permutations, so it can support 19 modes specified in the WiMAX system. Furthermore, an efficient algorithm to generate the control signals for all the 2 × 2 switches in this network is derived, which can reduce the hardware complexity and overall latency of the modified Benes network. Synthesis results show that the proposed control signal generator can save 25.4% chip area and the overall network latency can be reduced by 36. 2%.展开更多
In this paper,it has proposed a realtime implementation of low-density paritycheck(LDPC) decoder with less complexity used for satellite communication on FPGA platform.By adopting a(2048.4096)irregular quasi-cyclic(QC...In this paper,it has proposed a realtime implementation of low-density paritycheck(LDPC) decoder with less complexity used for satellite communication on FPGA platform.By adopting a(2048.4096)irregular quasi-cyclic(QC) LDPC code,the proposed partly parallel decoding structure balances the complexity between the check node unit(CNU) and the variable node unit(VNU) based on min-sum(MS) algorithm,thereby achieving less Slice resources and superior clock performance.Moreover,as a lookup table(LUT) is utilized in this paper to search the node message stored in timeshare memory unit,it is simple to reuse and save large amount of storage resources.The implementation results on Xilinx FPGA chip illustrate that,compared with conventional structure,the proposed scheme can achieve at last 28.6%and 8%cost reduction in RAM and Slice respectively.The clock frequency is also increased to 280 MHz without decoding performance deterioration and convergence speed reduction.展开更多
Non-binary low density parity check （NB-LDPC） codes are considered as preferred candidate in conditions where short/medium codeword length codes and better performance at low signal to noise ratios （SNR） are requi...Non-binary low density parity check （NB-LDPC） codes are considered as preferred candidate in conditions where short/medium codeword length codes and better performance at low signal to noise ratios （SNR） are required. They have better burst error correcting performance, especially with high order Galois fields （GF）. A shared comparator （SCOMP） architecture for elementary of check node （ECN）/elementary of variable node （EVN） to reduce decoder complexity is introduced because high complexity of check node （CN） and variable node （VN） prevent NB-LDPC decoder from widely applications. The decoder over GF（16） is based on the extended rain-sum （EMS） algorithm. The decoder matrix is an irregular structure as it can provide better performance than regular ones. In order to provide higher throughput and increase the parallel processing efficiency, the clock which is 8 times of the system frequency is adopted in this paper to drive the CN/VN modules. The decoder complexity can be reduced by 28% from traditional decoder when SCOMP architecture is introduced. The result of synthesis software shows that the throughput can achieve 34 Mbit/s at 10 iterations. The proposed architecture can be conveniently extended to GF such as GF（64） or GF（256）. Compared with previous works, the decoder proposed in this paper has better hardware efficiency for practical applications.展开更多
In this paper, we focus on shortblock nonbinary LDPC(NB-LDPC) codes based on cyclic codes. Based on Tanner graphs' isomorphism, we present an efficient search algorithm for finding non-isomorphic binary cyclic LDP...In this paper, we focus on shortblock nonbinary LDPC(NB-LDPC) codes based on cyclic codes. Based on Tanner graphs' isomorphism, we present an efficient search algorithm for finding non-isomorphic binary cyclic LDPC codes. Notice that the parity-check matrix H of the resulting code is square and not of full rank, and its row weight and column weight are the same. By replacing the ones in the same column of H with a nonzero element of fi nite fi elds GF(q), a class of NB-LDPC codes over GF(q) is obtained. Numerical results show that the constructed codes perform well over the AWGN channel and have fast decoding convergence. Therefore, the proposed NB-LDPC codes provide a promising coding scheme for low-latency and high-reliability communications.展开更多
Digital low-density parity-check(LDPC) decoders can hardly meet the power-limits brought by the new application scenarios. The analog LDPC decoder, which is an application of the analog computation technology, is cons...Digital low-density parity-check(LDPC) decoders can hardly meet the power-limits brought by the new application scenarios. The analog LDPC decoder, which is an application of the analog computation technology, is considered to have the potential to address this issue to some extent. However, due to the lack of automation tools and analog stopping criteria, the analog LDPC decoders suffer from costly handcraft design and additional decoding delay, and are not feasible to practical applications. To address these issues, a decoder architecture using reusable building blocks is designed to lower the handcraft design, and a probability stopping criterion that is specially designed for analog decoder is further planned and implemented to reduce the decoding delay. Then, a(480,240) CMOS analog LDPC decoder is designed and fabricated in a 0.35-μm CMOS technology. Experimental results show that the decoder prototype can achieve 50 Mbps throughput when the power consumption is about 86.3m W, and the decoding delay can be reduced by at most 93% compared with using the preset maximum decoding delay in existing works.展开更多
When implementing helicopter-satellite communications, periodical interruption of the received signal is a challenging problem because the communication antenna is intermittently blocked by the rotating blades of the ...When implementing helicopter-satellite communications, periodical interruption of the received signal is a challenging problem because the communication antenna is intermittently blocked by the rotating blades of the helicopter. The helicopter-satellite channel model and the Forward Error Control（FEC） coding countermeasure are presented in this paper. On the basis of this model, Check-Hybrid（CH） Low-Density Parity-Check（LDPC）codes are designed to mitigate the periodical blockage over the helicopter-satellite channels. The CH-LDPC code is derived by replacing part of single parity-check code constraints in a Quasi-Cyclic LDPC（QC-LDPC） code by using more powerful linear block code constraints. In particular, a method of optimizing the CH-LDPC code ensemble by searching the best matching component code among a variety of linear block codes using extrinsic information transfer charts is proposed. Simulation results show that, the CH-LDPC coding scheme designed for the helicopter-satellite channels in this paper achieves more than 25% bandwidth efficiency improvement, compared with the FEC scheme that uses QC-LDPC codes.展开更多
基金The National Natural Science Foundation of China(No.60871079)
文摘A modified Benes network is proposed to be used as an optimal shuffle network in worldwide interoperability for microwave access （WiMAX） low density parity check （LDPC） decoders, When the size of the input is not a power of two, the modified Benes network can achieve the most optimal performance. This modified Benes network is non-blocking and can perform any sorts of permutations, so it can support 19 modes specified in the WiMAX system. Furthermore, an efficient algorithm to generate the control signals for all the 2 × 2 switches in this network is derived, which can reduce the hardware complexity and overall latency of the modified Benes network. Synthesis results show that the proposed control signal generator can save 25.4% chip area and the overall network latency can be reduced by 36. 2%.
文摘In this paper,it has proposed a realtime implementation of low-density paritycheck(LDPC) decoder with less complexity used for satellite communication on FPGA platform.By adopting a(2048.4096)irregular quasi-cyclic(QC) LDPC code,the proposed partly parallel decoding structure balances the complexity between the check node unit(CNU) and the variable node unit(VNU) based on min-sum(MS) algorithm,thereby achieving less Slice resources and superior clock performance.Moreover,as a lookup table(LUT) is utilized in this paper to search the node message stored in timeshare memory unit,it is simple to reuse and save large amount of storage resources.The implementation results on Xilinx FPGA chip illustrate that,compared with conventional structure,the proposed scheme can achieve at last 28.6%and 8%cost reduction in RAM and Slice respectively.The clock frequency is also increased to 280 MHz without decoding performance deterioration and convergence speed reduction.
基金supported by the Foundation of the Chinese Academy of Sciences (KGFZD-135-16-015)
文摘Non-binary low density parity check （NB-LDPC） codes are considered as preferred candidate in conditions where short/medium codeword length codes and better performance at low signal to noise ratios （SNR） are required. They have better burst error correcting performance, especially with high order Galois fields （GF）. A shared comparator （SCOMP） architecture for elementary of check node （ECN）/elementary of variable node （EVN） to reduce decoder complexity is introduced because high complexity of check node （CN） and variable node （VN） prevent NB-LDPC decoder from widely applications. The decoder over GF（16） is based on the extended rain-sum （EMS） algorithm. The decoder matrix is an irregular structure as it can provide better performance than regular ones. In order to provide higher throughput and increase the parallel processing efficiency, the clock which is 8 times of the system frequency is adopted in this paper to drive the CN/VN modules. The decoder complexity can be reduced by 28% from traditional decoder when SCOMP architecture is introduced. The result of synthesis software shows that the throughput can achieve 34 Mbit/s at 10 iterations. The proposed architecture can be conveniently extended to GF such as GF（64） or GF（256）. Compared with previous works, the decoder proposed in this paper has better hardware efficiency for practical applications.
基金supported in part by National Natural Science Foundation of China under Grants 61372074,91438101,61103143,U1504601,and U1404622Key Scientific and Technological Project of Henan under Grants 162102310589 and 172102310124
文摘In this paper, we focus on shortblock nonbinary LDPC(NB-LDPC) codes based on cyclic codes. Based on Tanner graphs' isomorphism, we present an efficient search algorithm for finding non-isomorphic binary cyclic LDPC codes. Notice that the parity-check matrix H of the resulting code is square and not of full rank, and its row weight and column weight are the same. By replacing the ones in the same column of H with a nonzero element of fi nite fi elds GF(q), a class of NB-LDPC codes over GF(q) is obtained. Numerical results show that the constructed codes perform well over the AWGN channel and have fast decoding convergence. Therefore, the proposed NB-LDPC codes provide a promising coding scheme for low-latency and high-reliability communications.
基金supported in part by the National Natural Science Foundation of China(No.61601027)the Opening Fund of the Space Objective Measure Key Laboratory(No.2016011)
文摘Digital low-density parity-check(LDPC) decoders can hardly meet the power-limits brought by the new application scenarios. The analog LDPC decoder, which is an application of the analog computation technology, is considered to have the potential to address this issue to some extent. However, due to the lack of automation tools and analog stopping criteria, the analog LDPC decoders suffer from costly handcraft design and additional decoding delay, and are not feasible to practical applications. To address these issues, a decoder architecture using reusable building blocks is designed to lower the handcraft design, and a probability stopping criterion that is specially designed for analog decoder is further planned and implemented to reduce the decoding delay. Then, a(480,240) CMOS analog LDPC decoder is designed and fabricated in a 0.35-μm CMOS technology. Experimental results show that the decoder prototype can achieve 50 Mbps throughput when the power consumption is about 86.3m W, and the decoding delay can be reduced by at most 93% compared with using the preset maximum decoding delay in existing works.
基金supported by the National Natural Science Foundation of China(No.91538203)the new strategic industries development projects of Shenzhen City(No.JCYJ20150403155812833)
文摘When implementing helicopter-satellite communications, periodical interruption of the received signal is a challenging problem because the communication antenna is intermittently blocked by the rotating blades of the helicopter. The helicopter-satellite channel model and the Forward Error Control（FEC） coding countermeasure are presented in this paper. On the basis of this model, Check-Hybrid（CH） Low-Density Parity-Check（LDPC）codes are designed to mitigate the periodical blockage over the helicopter-satellite channels. The CH-LDPC code is derived by replacing part of single parity-check code constraints in a Quasi-Cyclic LDPC（QC-LDPC） code by using more powerful linear block code constraints. In particular, a method of optimizing the CH-LDPC code ensemble by searching the best matching component code among a variety of linear block codes using extrinsic information transfer charts is proposed. Simulation results show that, the CH-LDPC coding scheme designed for the helicopter-satellite channels in this paper achieves more than 25% bandwidth efficiency improvement, compared with the FEC scheme that uses QC-LDPC codes.
