A Monolithic integrated phase locked-loop （PLL） with a low phase noise is proposed in this paper. Several techniques are utilized to improve the performance of the PLL which works at the milli- meter-wave band. The ...A Monolithic integrated phase locked-loop （PLL） with a low phase noise is proposed in this paper. Several techniques are utilized to improve the performance of the PLL which works at the milli- meter-wave band. The on-chip high-Q eoplanar waveguides （CPWs） are utilized in the resonant tank and the differential current amplifier with a resonator is used to realize the VCO. In the output buffer circuit, several stages of cascaded source-followers connect and differential amplifiers are adopted to improve the driving capability of the PLL＇ s output signals. An improved analog multiplier topology is also used in the PD circuit to improve the gain of the PD. The proposed PLL is realized with a 0.2p, m GaAs pseudomorphie high electron mobility transistor （PHEMT） process. At 10 kHz offset from the center frequency, the measured output phase noise of the PLL output is only -88.83dBc/Hz. The circuit exhibits a low root mean sauare （RMS） litter of 1.68Ds.展开更多
We demonstrated a scheme of phase-locked terahertz quantum cascade lasers(THz QCLs)array,with a single-mode pulse power of 108 mW at 13 K.The device utilizes a Talbot cavity to achieve phase locking among five ridge l...We demonstrated a scheme of phase-locked terahertz quantum cascade lasers(THz QCLs)array,with a single-mode pulse power of 108 mW at 13 K.The device utilizes a Talbot cavity to achieve phase locking among five ridge lasers with first-order buried distributed feedback(DFB)grating,resulting in nearly five times amplification of the single-mode power.Due to the optimum length of Talbot cavity depends on wavelength,the combination of Talbot cavity with the DFB grating leads to better power amplification than the combination with multimode Fabry-Perot(F-P)cavities.The Talbot cavity facet reflects light back to the ridge array direction and achieves self-imaging in the array,enabling phase-locked operation of ridges.We set the spacing between adjacent elements to be 220μm,much larger than the free-space wavelength,ensuring the operation of the fundamental supermode throughout the laser's dynamic range and obtaining a high-brightness far-field distribution.This scheme provides a new approach for enhancing the single-mode power of THz QCLs.展开更多
An inexpensive MC4044-based phase locked loop for constant speed control of a DC motor is discussed. It operates on a principle similar to that of a frequency synthesizer. The paper introduces the system configuration...An inexpensive MC4044-based phase locked loop for constant speed control of a DC motor is discussed. It operates on a principle similar to that of a frequency synthesizer. The paper introduces the system configuration with a detailed description of its operating principle, some practical design considerations are discussed with an experimental study to test the control performance of the newly designed system. The experimental result shows that the phase locked control system can regulate the speed of a DC torque motor with a precision up to 0.0022%(1).[展开更多
In deep space exploration,many engineering and scientific requirements require the accuracy of the measured Doppler frequency to be as high as possible.In our paper,we analyze the possible frequency measurement points...In deep space exploration,many engineering and scientific requirements require the accuracy of the measured Doppler frequency to be as high as possible.In our paper,we analyze the possible frequency measurement points of the third-order phase-locked loop(PLL)and find a new Doppler measurement strategy.Based on this finding,a Doppler frequency measurement algorithm with significantly higher measurement accuracy is obtained.In the actual data processing,compared with the existing engineering software,the accuracy of frequency of 1 second integration is about 5.5 times higher when using the new algorithm.The improved algorithm is simple and easy to implement.This improvement can be easily combined with other improvement methods of PLL,so that the performance of PLL can be further improved.展开更多
A low jitter All-Digital Phase-Locked Loop （ADPLL） used as a clock generator is designed. The Digital-Controlled Oscillator （DCO） for this ADPLL is a seven-stage ring oscillator with the delay of each stage change...A low jitter All-Digital Phase-Locked Loop （ADPLL） used as a clock generator is designed. The Digital-Controlled Oscillator （DCO） for this ADPLL is a seven-stage ring oscillator with the delay of each stage changeable. Based on the Impulse Sensitivity Function （ISF） analysis, an effective way is proposed to reduce the ADPLL＇s jitter by the careful design of the sizes of the inverters used in the DCO with a simple architecture other than a complex one. The ADPLL is implemented in a 0.18μm CMOS process with 1.SV supply voltage, occupies 0.046mm^2 of on-chip area. According to the measured results, the ADPLL can operate from 108MHz to 304MHz, and the peak-to-peak jitter is 139ps when the DCO＇s output frequency is 188MHz.展开更多
In [1] and [2], the authors made a deep qualitative analysis of the equationwith the character of tangent detected phase and they mathematically provided atheoretical basis of why the phase looked loop has no look--lo...In [1] and [2], the authors made a deep qualitative analysis of the equationwith the character of tangent detected phase and they mathematically provided atheoretical basis of why the phase looked loop has no look--losing point. However,according to many practical experts, it is rather difficult to put such a phaselooked loop into practice, though it has fine properties. W. C. Lindsey [3] made a展开更多
Truncation manipulation is a simple but effective way to improve the intensity distribution properties of the phase-locked Gaussian beam array at the receiving plane. In this paper, the analytical expression for the p...Truncation manipulation is a simple but effective way to improve the intensity distribution properties of the phase-locked Gaussian beam array at the receiving plane. In this paper, the analytical expression for the propagation of the phase-locked truncated Gaussian beam array in a turbulent atmosphere is obtained based on the extended Huygens--Fresnel principle. Power in the diffraction-limited bucket is introduced as the beam quality factor to evaluate the influence of different truncation parameters. The dependence of optimal truncation ratio on the number of beamlets, the intensity of turbulence, propagation distance and laser wavelength is calculated and discussed. It is revealed that the optimal truncation ratio is larger for the laser array that contains more lasers, and the optimal truncation ratio will shift to a larger value with an increase in propagation distance and decrease in intensity of atmosphere turbulence. The optimal truncation ratio is independent of laser wavelength.展开更多
A diode laser array(DLA)positioned in an external cavity can receive the radiations emitted from its neighboring elements (C 1) and that of itself (S) after being reflected at the DLA facet as well as from the externa...A diode laser array(DLA)positioned in an external cavity can receive the radiations emitted from its neighboring elements (C 1) and that of itself (S) after being reflected at the DLA facet as well as from the external mirror (C 0). Considering the fact that｜C 0/S｜ should be larger than unity if the external cavity is effective,and｜C 1/S｜ should be larger than unity if the phase locking may be established in the external cavity.The requirements on the reflection at the facet of the diode laser array have been specified in terms of the cavity length and reflection coefficient of the external mirror.展开更多
Using a newly reported Pacific sea surface temperature data set, we extend a prior study that assigned El Niño episodes to distinct sequences. Within these sequences the episodes are phase-locked to subharmoni...Using a newly reported Pacific sea surface temperature data set, we extend a prior study that assigned El Niño episodes to distinct sequences. Within these sequences the episodes are phase-locked to subharmonics of the annual solar irradiance cycle having two- or three-year periodicity. There are 40 El Niño episodes occurring since 1872, each found within one of eighteen such sequences. Our list includes all previously reported events. Three El Niño episodes have already been observed in boreal winters of 2009, 2012 and 2015, illustrating a sequence of 3-year intervals that began in 2008. If the climate system remains in this state, the next El Niño is likely to occur in boreal winter of 2018.展开更多
A fast-locking, low-jitter, phase-locked loop （PLL） with a simple phase-frequency detector is proposed. The phase-frequency detector is composed of only two XOR gates. It simultaneously achieves low jitter and short...A fast-locking, low-jitter, phase-locked loop （PLL） with a simple phase-frequency detector is proposed. The phase-frequency detector is composed of only two XOR gates. It simultaneously achieves low jitter and short locking time. The voltage-controlled oscillator within the PLL consists of four-stage ring oscillators which are coupled to each other and oscillate with the same frequency and a phase shift of 45. The PLL is fabricated in 0. 1Stem CMOS technology. The measured phase noise of the PLL output at 500kHz offset from the 5GHz center frequency is - 102.6dBc/Hz. The circuit exhibits a capture range of 280MHz and a low RMS jitter of 2.06ps. The power dissipation excluding the output buffers is only 21.6roW at a 1.8V supply.展开更多
The paper presents a kind of transmission system which employs M-ary Position Phase Shift Keying(MPPSK) to send data and Phase Locked Loop(PLL) based techniques for data retrieve.With a single PLL, MPPSK demodulation ...The paper presents a kind of transmission system which employs M-ary Position Phase Shift Keying(MPPSK) to send data and Phase Locked Loop(PLL) based techniques for data retrieve.With a single PLL, MPPSK demodulation is achieved, as well as carrier recovery and symbol synchronization.Firstly, MPPSK modulation method is briefly introduced.2PPSK's PSD expression is given with its optimization result.Orthogonal Phase Detector(PD) and static threshold are used for the purpose of wider phase range and simplicity in demodulation.The data rate is alterable, which is 4.65 kbps for 2PPSK and 9.3 kbps for 4PPSK in the paper.Then some indicative comparisons in Signal to Noise Ratio Symbol Error Rate(SNR-SER) are made among 2PPSK, 3PPSK and 4PPSK, of which 4PPSK has proved to be optimal in ten slots each symbol conditions.And finally, it is demonstrated by system simulations that lower than 10-4 Symbol Error Rate(SER) performance can be obtained at 13 dB symbol SNR.展开更多
This paper presents a single-phase Z-source inverter as a power conditioning system for a single phase utility connected system. Z-source inverter is a single-stage topology that has buck-boost feature, which is possi...This paper presents a single-phase Z-source inverter as a power conditioning system for a single phase utility connected system. Z-source inverter is a single-stage topology that has buck-boost feature, which is possible because of additional shoot through state introduced in zero state of the conventional inverter pulse width modulation and provides desired output AC voltage. Small distributed generation （DG） system with alternate energy sources requires power conditioning units with low cost, high efficiency and tolerance to wide range of input voltage variation and has to perform various functions such as dc-ac conversion, system control and achieve power quality norms. To meet some of these requirements a two-loop control strategy for ac side control with grid current feedback with PI control and inner filter capacitor current feedback with proportional control and on dc side PID control for Z-source capacitor voltage regulation are employed, which gives good transient response also suppress load and source disturbances effectively. Theoretical analysis of proposed scheme is established and then simulation results are presented to validate proposed control strategy.展开更多
The sea surface temperature （SST） anomaly of the eastern Indian Ocean （EIO） exhibits cold anomalies in the boreal summer or fall during E1 Nino development years and warm anomalies in winter or spring following th...The sea surface temperature （SST） anomaly of the eastern Indian Ocean （EIO） exhibits cold anomalies in the boreal summer or fall during E1 Nino development years and warm anomalies in winter or spring following the E1 Nino events. There also tend to be warm anomalies in the boreal summer or fall during La Nina development years and cold anomalies in winter or spring following the La Nina events. The seasonal phase-locking of SST change in the EIO associated with E1 Nino/Southern Oscillation is linked to the variability of convection over the maritime continent, which induces an atmospheric Rossby wave over the EIO. Local air-sea interaction exerts different effects on SST anomalies, depending on the relationship between the Rossby wave and the mean flow related to the seasonal migration of the buffer zone, which shifts across the equator between summer and winter. The summer cold events start with cooling in the Timor Sea, together with increasing easterly flow along the equator. Negative SST anomalies develop near Sumatra, through the interaction between the atmospheric Rossby wave and the underneath sea surface. These SST anomalies are also contributed to by the increased upwelling of the mixed layer and the equatorward temperature advection in the boreal fall. As the buffer zone shifts across the equator towards boreal winter, the anomalous easterly flow tends to weaken the mean flow near the equator, and the EIO SST increases due to the reduction of latent heat flux from the sea surface. As a result, wintertime SST anomalies appear with a uniform and nearly basin-wide pattern beneath the easterly anomalies. These SST anomalies are also caused by the increase in solar radiation associated with the anticyclonic atmospheric Rossby wave over the EIO. Similarly, the physical processes of the summer warm events, which are followed by wintertime cold SST anomalies, can be explained by the changes in atmospheric and oceanic fields with opposite signs to those anomalies described above.展开更多
The mechanism of the locking of the E1 Nino event onset phase to boreal spring （from April to June） in an intermediate coupled ocean-atmosphere model is investigated. The results show that the seasonal variation of ...The mechanism of the locking of the E1 Nino event onset phase to boreal spring （from April to June） in an intermediate coupled ocean-atmosphere model is investigated. The results show that the seasonal variation of the zonal wind anomaly over the equatorial Pacific associated with the seasonal variation of the ITCZ is the mechanism of the locking in the model. From January to March of the E1 Nino year, the western wind anomaly over the western equatorial Pacific can excite the downwelling Kelvin wave that propagates eastward to the eastern and middle Pacific by April to June. From April to December of the year before the E1 Nifio year, the eastern wind anomaly over the equatorial Pacific forces the downwelling Rossby waves that modulate the ENSO cycle. The modulation and the reflection at the western boundary modulate the time of the transition from the cool to the warm phase to September of the year before the E1 Nifio year and cause the strongest downwelling Kelvin wave from the reflected Rossby waves at the western boundary to arrive in the middle and eastern equatorial Pacific by April to June of the E1 Nino year. The superposition of these two kinds of downwelling Kelvin waves causes the El Nino event to tend to occur from April to June.展开更多
The relation of interannual anomaly of East Asian monsoon to the ENSO cycle is investigated in terms of even and odd symmetry analysis over a tropical heating field based on the past 30-year data. Evidence suggests th...The relation of interannual anomaly of East Asian monsoon to the ENSO cycle is investigated in terms of even and odd symmetry analysis over a tropical heating field based on the past 30-year data. Evidence suggests that odd and even symmetry components related to the monsoon and Walker heating, respectively, effectively describe the East Asian monsoon circulation and Pacific Walker analog, with the monsoon intensity index corresponding to its heating vigor and western Pacific Walker heating vigor to ENSO phase change, both types of heating marked by pronounced seasonal variation and phase-locking; the key region for linking monsoon-ENSO interaction is the western Pacific warm pool; the monsoon effect upon ENSO cycle is affected jointly by the seasonal evolution and interannual anomaly of the heating components; the superimposition of an anti-Walker circulation phase produced by interannual winter monsoon perturbation upon a weaker Walker phase on a seasonal basis leads to an El Nino happening in March-April and plays a significant role in maintaining a warm ENSO phase.展开更多
The phase-locking dynamics in 1D and 2D lattices of non-identical coupled circle maps is explored. Aglobal phase locking can be attained via a cascade of clustering processes with the increase of the coupling strength...The phase-locking dynamics in 1D and 2D lattices of non-identical coupled circle maps is explored. Aglobal phase locking can be attained via a cascade of clustering processes with the increase of the coupling strength.Collective spatiotemporal dynamics is observed when a global phase locking is reached. Crisis-induced desynchronizationis found, and its consequent spatiotemporal chaos is studied.展开更多
This work summarizes the structure and operating features of a high-performance 3-stage dual-delay-path (DDP) voltage-controlled ring oscillator (VCRO) with self-biased delay cells for Phase-Locked Loop (PLL) structur...This work summarizes the structure and operating features of a high-performance 3-stage dual-delay-path (DDP) voltage-controlled ring oscillator (VCRO) with self-biased delay cells for Phase-Locked Loop (PLL) structurebased clock generation and digital system driving. For a voltage supply V<sub>DD</sub> = 1.8 V, the resulting set of performance parameters include power consumption P<sub><sub></sub>DC</sub> = 4.68 mW and phase noise PN@1MHz = -107.8 dBc/Hz. From the trade-off involving P<sub>DC</sub> and PN, a system level high performance is obtained considering a reference figure-of-merit ( FoM = -224 dBc/Hz ). Implemented at schematic level by applying CMOS-based technology (UMC L180), the proposed VCRO was designed at Cadence environment and optimized at MunEDA WiCkeD tool.展开更多
A 2.5Gb/s clock and data recovery （CDR） circuit is designed and realized in TSMC＇s standard 0.18/μm CMOS process. The clock recovery is based on a PLL. For phase noise optimization,a dynamic phase and frequency de...A 2.5Gb/s clock and data recovery （CDR） circuit is designed and realized in TSMC＇s standard 0.18/μm CMOS process. The clock recovery is based on a PLL. For phase noise optimization,a dynamic phase and frequency detector （PFD） is used in the PLL. The rms jitter of the recovered 2.5GHz clock is 2.4ps and the SSB phase noise is - 111dBc/Hz at 10kHz offset. The rms jitter of the recovered 2.5Gb/s data is 3.3ps. The power consumption is 120mW.展开更多
A design and implementation for a 2.4GHz quadrature output frequency synthesizer intended for bluetooth in 0. 35μm CMOS technology are presented. A differentially controlled quadrature voltage-controlled oscillator ...A design and implementation for a 2.4GHz quadrature output frequency synthesizer intended for bluetooth in 0. 35μm CMOS technology are presented. A differentially controlled quadrature voltage-controlled oscillator （QVCO） is employed to generate quadrature （I/Q） signals. A second-order loop filter, with a unit gain transconductance amplifier having the performance of a third-order loop filter,is exploited for low cost. The measured spot phase noise is -106.15dBc/Hz@ 1MHz. Close-in phase noise is less than -70dBc/Hz. The synthesizer consumes 13.5mA under a 3.3V voltage supply. The core size is 1.3mm×0. 8mm.展开更多
A fractional-N frequency synthesizer for 433/868MHz SRD applications is implemented in a 0.3μm CMOS process. A wide-band VCO and an AFC are used to cover the desired bands. A 3bit third order sigma-delta modulator is...A fractional-N frequency synthesizer for 433/868MHz SRD applications is implemented in a 0.3μm CMOS process. A wide-band VCO and an AFC are used to cover the desired bands. A 3bit third order sigma-delta modulator is adopted to reduce the out-band phase noise. The measurements show a VCO tuning range from 1.31 to 1.88GHz with AFC working correctly,an out-band phase noise of -139dBc/Hz at 3MHz offset frequency, and a fractional spur of less than - 60dBc. The chip area is 1.5mm × 1.2mm and the total current dissipation including LO buffers is 19mA from a single 3.0V supply voltage.展开更多
基金Supported by the National Natural Science Foundation of China （No. 61106024, 60901012, 60976029） , the National High Technology Research and Development Program of China （No. 2011AA010301 ）, and the Science and Technology Program of Southeast University （No. K J2010402 ）.
文摘A Monolithic integrated phase locked-loop （PLL） with a low phase noise is proposed in this paper. Several techniques are utilized to improve the performance of the PLL which works at the milli- meter-wave band. The on-chip high-Q eoplanar waveguides （CPWs） are utilized in the resonant tank and the differential current amplifier with a resonator is used to realize the VCO. In the output buffer circuit, several stages of cascaded source-followers connect and differential amplifiers are adopted to improve the driving capability of the PLL＇ s output signals. An improved analog multiplier topology is also used in the PD circuit to improve the gain of the PD. The proposed PLL is realized with a 0.2p, m GaAs pseudomorphie high electron mobility transistor （PHEMT） process. At 10 kHz offset from the center frequency, the measured output phase noise of the PLL output is only -88.83dBc/Hz. The circuit exhibits a low root mean sauare （RMS） litter of 1.68Ds.
基金funded by National Natural Science Foundation of China, grant numbers 62335006, 62274014, 62235016, 61734006, 61835011, 61991430funded by Key Program of the Chinese Academy of Sciences, grant numbers XDB43000000, QYZDJSSW-JSC027Beijing Municipal Science & Technology Commission, grant number Z221100002722018
文摘We demonstrated a scheme of phase-locked terahertz quantum cascade lasers(THz QCLs)array,with a single-mode pulse power of 108 mW at 13 K.The device utilizes a Talbot cavity to achieve phase locking among five ridge lasers with first-order buried distributed feedback(DFB)grating,resulting in nearly five times amplification of the single-mode power.Due to the optimum length of Talbot cavity depends on wavelength,the combination of Talbot cavity with the DFB grating leads to better power amplification than the combination with multimode Fabry-Perot(F-P)cavities.The Talbot cavity facet reflects light back to the ridge array direction and achieves self-imaging in the array,enabling phase-locked operation of ridges.We set the spacing between adjacent elements to be 220μm,much larger than the free-space wavelength,ensuring the operation of the fundamental supermode throughout the laser's dynamic range and obtaining a high-brightness far-field distribution.This scheme provides a new approach for enhancing the single-mode power of THz QCLs.
文摘An inexpensive MC4044-based phase locked loop for constant speed control of a DC motor is discussed. It operates on a principle similar to that of a frequency synthesizer. The paper introduces the system configuration with a detailed description of its operating principle, some practical design considerations are discussed with an experimental study to test the control performance of the newly designed system. The experimental result shows that the phase locked control system can regulate the speed of a DC torque motor with a precision up to 0.0022%(1).[
基金supported by the National Natural Science Foundation of China(Grant Nos.11773060,11973074,U1831137 and 11703070)National Key Basic Research and Development Program(2018YFA0404702)+1 种基金Shanghai Key Laboratory of Space Navigation and Positioning(3912DZ227330001)the Key Laboratory for Radio Astronomy of CAS。
文摘In deep space exploration,many engineering and scientific requirements require the accuracy of the measured Doppler frequency to be as high as possible.In our paper,we analyze the possible frequency measurement points of the third-order phase-locked loop(PLL)and find a new Doppler measurement strategy.Based on this finding,a Doppler frequency measurement algorithm with significantly higher measurement accuracy is obtained.In the actual data processing,compared with the existing engineering software,the accuracy of frequency of 1 second integration is about 5.5 times higher when using the new algorithm.The improved algorithm is simple and easy to implement.This improvement can be easily combined with other improvement methods of PLL,so that the performance of PLL can be further improved.
文摘A low jitter All-Digital Phase-Locked Loop （ADPLL） used as a clock generator is designed. The Digital-Controlled Oscillator （DCO） for this ADPLL is a seven-stage ring oscillator with the delay of each stage changeable. Based on the Impulse Sensitivity Function （ISF） analysis, an effective way is proposed to reduce the ADPLL＇s jitter by the careful design of the sizes of the inverters used in the DCO with a simple architecture other than a complex one. The ADPLL is implemented in a 0.18μm CMOS process with 1.SV supply voltage, occupies 0.046mm^2 of on-chip area. According to the measured results, the ADPLL can operate from 108MHz to 304MHz, and the peak-to-peak jitter is 139ps when the DCO＇s output frequency is 188MHz.
文摘In [1] and [2], the authors made a deep qualitative analysis of the equationwith the character of tangent detected phase and they mathematically provided atheoretical basis of why the phase looked loop has no look--losing point. However,according to many practical experts, it is rather difficult to put such a phaselooked loop into practice, though it has fine properties. W. C. Lindsey [3] made a
基金supported by the Innovation Foundation for Postgraduate of Hunan Province
文摘Truncation manipulation is a simple but effective way to improve the intensity distribution properties of the phase-locked Gaussian beam array at the receiving plane. In this paper, the analytical expression for the propagation of the phase-locked truncated Gaussian beam array in a turbulent atmosphere is obtained based on the extended Huygens--Fresnel principle. Power in the diffraction-limited bucket is introduced as the beam quality factor to evaluate the influence of different truncation parameters. The dependence of optimal truncation ratio on the number of beamlets, the intensity of turbulence, propagation distance and laser wavelength is calculated and discussed. It is revealed that the optimal truncation ratio is larger for the laser array that contains more lasers, and the optimal truncation ratio will shift to a larger value with an increase in propagation distance and decrease in intensity of atmosphere turbulence. The optimal truncation ratio is independent of laser wavelength.
文摘A diode laser array(DLA)positioned in an external cavity can receive the radiations emitted from its neighboring elements (C 1) and that of itself (S) after being reflected at the DLA facet as well as from the external mirror (C 0). Considering the fact that｜C 0/S｜ should be larger than unity if the external cavity is effective,and｜C 1/S｜ should be larger than unity if the phase locking may be established in the external cavity.The requirements on the reflection at the facet of the diode laser array have been specified in terms of the cavity length and reflection coefficient of the external mirror.
文摘Using a newly reported Pacific sea surface temperature data set, we extend a prior study that assigned El Niño episodes to distinct sequences. Within these sequences the episodes are phase-locked to subharmonics of the annual solar irradiance cycle having two- or three-year periodicity. There are 40 El Niño episodes occurring since 1872, each found within one of eighteen such sequences. Our list includes all previously reported events. Three El Niño episodes have already been observed in boreal winters of 2009, 2012 and 2015, illustrating a sequence of 3-year intervals that began in 2008. If the climate system remains in this state, the next El Niño is likely to occur in boreal winter of 2018.
文摘A fast-locking, low-jitter, phase-locked loop （PLL） with a simple phase-frequency detector is proposed. The phase-frequency detector is composed of only two XOR gates. It simultaneously achieves low jitter and short locking time. The voltage-controlled oscillator within the PLL consists of four-stage ring oscillators which are coupled to each other and oscillate with the same frequency and a phase shift of 45. The PLL is fabricated in 0. 1Stem CMOS technology. The measured phase noise of the PLL output at 500kHz offset from the 5GHz center frequency is - 102.6dBc/Hz. The circuit exhibits a capture range of 280MHz and a low RMS jitter of 2.06ps. The power dissipation excluding the output buffers is only 21.6roW at a 1.8V supply.
基金Supported by National Natural Science Foundation of China (60472054)
文摘The paper presents a kind of transmission system which employs M-ary Position Phase Shift Keying(MPPSK) to send data and Phase Locked Loop(PLL) based techniques for data retrieve.With a single PLL, MPPSK demodulation is achieved, as well as carrier recovery and symbol synchronization.Firstly, MPPSK modulation method is briefly introduced.2PPSK's PSD expression is given with its optimization result.Orthogonal Phase Detector(PD) and static threshold are used for the purpose of wider phase range and simplicity in demodulation.The data rate is alterable, which is 4.65 kbps for 2PPSK and 9.3 kbps for 4PPSK in the paper.Then some indicative comparisons in Signal to Noise Ratio Symbol Error Rate(SNR-SER) are made among 2PPSK, 3PPSK and 4PPSK, of which 4PPSK has proved to be optimal in ten slots each symbol conditions.And finally, it is demonstrated by system simulations that lower than 10-4 Symbol Error Rate(SER) performance can be obtained at 13 dB symbol SNR.
文摘This paper presents a single-phase Z-source inverter as a power conditioning system for a single phase utility connected system. Z-source inverter is a single-stage topology that has buck-boost feature, which is possible because of additional shoot through state introduced in zero state of the conventional inverter pulse width modulation and provides desired output AC voltage. Small distributed generation （DG） system with alternate energy sources requires power conditioning units with low cost, high efficiency and tolerance to wide range of input voltage variation and has to perform various functions such as dc-ac conversion, system control and achieve power quality norms. To meet some of these requirements a two-loop control strategy for ac side control with grid current feedback with PI control and inner filter capacitor current feedback with proportional control and on dc side PID control for Z-source capacitor voltage regulation are employed, which gives good transient response also suppress load and source disturbances effectively. Theoretical analysis of proposed scheme is established and then simulation results are presented to validate proposed control strategy.
文摘The sea surface temperature （SST） anomaly of the eastern Indian Ocean （EIO） exhibits cold anomalies in the boreal summer or fall during E1 Nino development years and warm anomalies in winter or spring following the E1 Nino events. There also tend to be warm anomalies in the boreal summer or fall during La Nina development years and cold anomalies in winter or spring following the La Nina events. The seasonal phase-locking of SST change in the EIO associated with E1 Nino/Southern Oscillation is linked to the variability of convection over the maritime continent, which induces an atmospheric Rossby wave over the EIO. Local air-sea interaction exerts different effects on SST anomalies, depending on the relationship between the Rossby wave and the mean flow related to the seasonal migration of the buffer zone, which shifts across the equator between summer and winter. The summer cold events start with cooling in the Timor Sea, together with increasing easterly flow along the equator. Negative SST anomalies develop near Sumatra, through the interaction between the atmospheric Rossby wave and the underneath sea surface. These SST anomalies are also contributed to by the increased upwelling of the mixed layer and the equatorward temperature advection in the boreal fall. As the buffer zone shifts across the equator towards boreal winter, the anomalous easterly flow tends to weaken the mean flow near the equator, and the EIO SST increases due to the reduction of latent heat flux from the sea surface. As a result, wintertime SST anomalies appear with a uniform and nearly basin-wide pattern beneath the easterly anomalies. These SST anomalies are also caused by the increase in solar radiation associated with the anticyclonic atmospheric Rossby wave over the EIO. Similarly, the physical processes of the summer warm events, which are followed by wintertime cold SST anomalies, can be explained by the changes in atmospheric and oceanic fields with opposite signs to those anomalies described above.
基金This work was supported by The National Key Basic Reserch and Development Project of China(2004CB418303)Project 4023100 of the Major Research Program for Global Change and Regional ResponseNational Natural Science Foundation of China(Grant No.40231005).
文摘The mechanism of the locking of the E1 Nino event onset phase to boreal spring （from April to June） in an intermediate coupled ocean-atmosphere model is investigated. The results show that the seasonal variation of the zonal wind anomaly over the equatorial Pacific associated with the seasonal variation of the ITCZ is the mechanism of the locking in the model. From January to March of the E1 Nino year, the western wind anomaly over the western equatorial Pacific can excite the downwelling Kelvin wave that propagates eastward to the eastern and middle Pacific by April to June. From April to December of the year before the E1 Nifio year, the eastern wind anomaly over the equatorial Pacific forces the downwelling Rossby waves that modulate the ENSO cycle. The modulation and the reflection at the western boundary modulate the time of the transition from the cool to the warm phase to September of the year before the E1 Nifio year and cause the strongest downwelling Kelvin wave from the reflected Rossby waves at the western boundary to arrive in the middle and eastern equatorial Pacific by April to June of the E1 Nino year. The superposition of these two kinds of downwelling Kelvin waves causes the El Nino event to tend to occur from April to June.
文摘The relation of interannual anomaly of East Asian monsoon to the ENSO cycle is investigated in terms of even and odd symmetry analysis over a tropical heating field based on the past 30-year data. Evidence suggests that odd and even symmetry components related to the monsoon and Walker heating, respectively, effectively describe the East Asian monsoon circulation and Pacific Walker analog, with the monsoon intensity index corresponding to its heating vigor and western Pacific Walker heating vigor to ENSO phase change, both types of heating marked by pronounced seasonal variation and phase-locking; the key region for linking monsoon-ENSO interaction is the western Pacific warm pool; the monsoon effect upon ENSO cycle is affected jointly by the seasonal evolution and interannual anomaly of the heating components; the superimposition of an anti-Walker circulation phase produced by interannual winter monsoon perturbation upon a weaker Walker phase on a seasonal basis leads to an El Nino happening in March-April and plays a significant role in maintaining a warm ENSO phase.
基金国家自然科学基金，国家重点基础研究发展计划(973计划)，高等学校全国优秀博士学位论文作者专项基金，the Teaching and Research Award Program for Outstanding Young Teachers in Higher Education,Institutions of MOE，HYD Foundation，教育部高校骨干教师资助计划
文摘The phase-locking dynamics in 1D and 2D lattices of non-identical coupled circle maps is explored. Aglobal phase locking can be attained via a cascade of clustering processes with the increase of the coupling strength.Collective spatiotemporal dynamics is observed when a global phase locking is reached. Crisis-induced desynchronizationis found, and its consequent spatiotemporal chaos is studied.
文摘This work summarizes the structure and operating features of a high-performance 3-stage dual-delay-path (DDP) voltage-controlled ring oscillator (VCRO) with self-biased delay cells for Phase-Locked Loop (PLL) structurebased clock generation and digital system driving. For a voltage supply V<sub>DD</sub> = 1.8 V, the resulting set of performance parameters include power consumption P<sub><sub></sub>DC</sub> = 4.68 mW and phase noise PN@1MHz = -107.8 dBc/Hz. From the trade-off involving P<sub>DC</sub> and PN, a system level high performance is obtained considering a reference figure-of-merit ( FoM = -224 dBc/Hz ). Implemented at schematic level by applying CMOS-based technology (UMC L180), the proposed VCRO was designed at Cadence environment and optimized at MunEDA WiCkeD tool.
文摘A 2.5Gb/s clock and data recovery （CDR） circuit is designed and realized in TSMC＇s standard 0.18/μm CMOS process. The clock recovery is based on a PLL. For phase noise optimization,a dynamic phase and frequency detector （PFD） is used in the PLL. The rms jitter of the recovered 2.5GHz clock is 2.4ps and the SSB phase noise is - 111dBc/Hz at 10kHz offset. The rms jitter of the recovered 2.5Gb/s data is 3.3ps. The power consumption is 120mW.
文摘A design and implementation for a 2.4GHz quadrature output frequency synthesizer intended for bluetooth in 0. 35μm CMOS technology are presented. A differentially controlled quadrature voltage-controlled oscillator （QVCO） is employed to generate quadrature （I/Q） signals. A second-order loop filter, with a unit gain transconductance amplifier having the performance of a third-order loop filter,is exploited for low cost. The measured spot phase noise is -106.15dBc/Hz@ 1MHz. Close-in phase noise is less than -70dBc/Hz. The synthesizer consumes 13.5mA under a 3.3V voltage supply. The core size is 1.3mm×0. 8mm.
文摘A fractional-N frequency synthesizer for 433/868MHz SRD applications is implemented in a 0.3μm CMOS process. A wide-band VCO and an AFC are used to cover the desired bands. A 3bit third order sigma-delta modulator is adopted to reduce the out-band phase noise. The measurements show a VCO tuning range from 1.31 to 1.88GHz with AFC working correctly,an out-band phase noise of -139dBc/Hz at 3MHz offset frequency, and a fractional spur of less than - 60dBc. The chip area is 1.5mm × 1.2mm and the total current dissipation including LO buffers is 19mA from a single 3.0V supply voltage.
