An intelligent fuzzy logic inference pipeline for the control of a dc-dc buck-boost converter was designed and built using a semi-custom VLSI chip. The fuzzy linguistics describing the switching topologies of the conv...An intelligent fuzzy logic inference pipeline for the control of a dc-dc buck-boost converter was designed and built using a semi-custom VLSI chip. The fuzzy linguistics describing the switching topologies of the converter was mapped into a look-up table that was synthesized into a set of Boolean equations. A VLSI chip–a field programmable gate array (FPGA) was used to implement the Boolean equations. Features include the size of RAM chip independent of number of rules in the knowledge base, on-chip fuzzification and defuzzification, faster response with speeds over giga fuzzy logic inferences per sec (FLIPS), and an inexpensive VLSI chip. The key application areas are: 1) on-chip integrated controllers;and 2) on-chip co-integration for entire system of sensors, circuits, controllers, and detectors for building complete instrument systems.展开更多
Programmable Logic Array (PLA) is an important building circuit of VLSI chips and some of the FPGA architectures have evolved from the basic PLA architectures. In this letter, a dynamic and static mixed PLA with singl...Programmable Logic Array (PLA) is an important building circuit of VLSI chips and some of the FPGA architectures have evolved from the basic PLA architectures. In this letter, a dynamic and static mixed PLA with single-phased clock is presented. Combining both dynamic and static design style rather than introducing additional interface-buffers overcomes the racing problem, thereby saves the chip area. Besides inheriting the advantages of dynamic circuit-low power dissipation and compact structure, this approach also provides high-speed operation.展开更多
This paper proposes a kind of programmable logic element(PLE)based on Sense-Switch pFLASH technology.By programming Sense-Switch pFLASH,all three-bit look-up table(LUT3)functions,partial four-bit look-up table(LUT4)fu...This paper proposes a kind of programmable logic element(PLE)based on Sense-Switch pFLASH technology.By programming Sense-Switch pFLASH,all three-bit look-up table(LUT3)functions,partial four-bit look-up table(LUT4)functions,latch functions,and d flip flop(DFF)with enable and reset functions can be realized.Because PLE uses a choice of operational logic(COOL)approach for the operation of logic functions,it allows any logic circuit to be implemented at any ratio of combinatorial logic to register.This intrinsic property makes it close to the basic application specific integrated circuit(ASIC)cell in terms of fine granularity,thus allowing ASIC-like cell-based mappers to apply all their optimization potential.By measuring Sense-Switch pFLASH and PLE circuits,the results show that the“on”state driving current of the Sense-Switch pFLASH is about 245.52μA,and that the“off”state leakage current is about 0.1 pA.The programmable function of PLE works normally.The delay of the typical combinatorial logic operation AND3 is 0.69 ns,and the delay of the sequential logic operation DFF is 0.65 ns,both of which meet the requirements of the design technical index.展开更多
Programmable logic array (PLA) is a popular structure for realizing arbitrary combinational networks. Easy test generation (ETG) PLA, a kind of PLA design with the property of easy test generation, is s PLA design wit...Programmable logic array (PLA) is a popular structure for realizing arbitrary combinational networks. Easy test generation (ETG) PLA, a kind of PLA design with the property of easy test generation, is s PLA design with added product terms and/or outputs such that tests are easy to generate, even no effort on test generation and fault simulation is necessary. This paper attempts to further clarify the concept of ETG circuits and extends the concepts of pseudo-nonconcurrency and separation to reduce the hardware overhead, based on a unified singlefault model. Experimental results show that the hardware overhead is generally less than 5%, which is considered to be the lowest cost for testable PLA designs.展开更多
High performance computer is often required by model predictive control(MPC) systems due to the heavy online computation burden.To extend MPC to more application cases with low-cost computation facilities, the impleme...High performance computer is often required by model predictive control(MPC) systems due to the heavy online computation burden.To extend MPC to more application cases with low-cost computation facilities, the implementation of MPC controller on field programmable gate array(FPGA) system is studied.For the dynamic matrix control(DMC) algorithm,the main design idea and the implemental strategy of DMC controller are introduced based on a FPGA’s embedded system.The performance tests show that both the computation efficiency and the accuracy of the proposed controller can be satisfied due to the parallel computing capability of FPGA.展开更多
Field Programmable Gate Array(FPGA) is an efficient reconfigurable integrated circuit platform and has become a core signal processing microchip device of digital systems over the last decade. With the rapid developme...Field Programmable Gate Array(FPGA) is an efficient reconfigurable integrated circuit platform and has become a core signal processing microchip device of digital systems over the last decade. With the rapid development of semiconductor technology, the performance and system integration of FPGA devices have been significantly progressed, and at the same time new challenges arise. The design of FPGA architecture is required to evolve to meet these challenges, while also taking advantage of ever increased microchip density. This survey reviews the recent development of advanced FPGA architectures, including improvement of the programming technologies, logic blocks, interconnects, and embedded resources. Moreover, some important emerging design issues of FPGA architectures, such as novel memory based FPGAs and 3D FPGAs, are also presented to provide an outlook for future FPGA development.展开更多
Introduces the characteristic of FPGA,motion estimation and full search block matching arithmetic,analyses collectivity configuration of basic working flow in ME and discusses in detall the control,computing and test ...Introduces the characteristic of FPGA,motion estimation and full search block matching arithmetic,analyses collectivity configuration of basic working flow in ME and discusses in detall the control,computing and test part of ME chip implementation.展开更多
Field programmable gate arrays （FPGAs） have wide and extensive applications in many areas. Due to programmable feature of FPGAs, faults of FPGAs can be easily tolerated if fault sites can be located. A hardware/soft...Field programmable gate arrays （FPGAs） have wide and extensive applications in many areas. Due to programmable feature of FPGAs, faults of FPGAs can be easily tolerated if fault sites can be located. A hardware/software （HW/SW） co-verification technique for FPGA test is proposed in this paper. Taking advantage of flexibility and observability of software in conjunction with high-speed simulation of hardware, this technique is capable of testing each input/output block （IOB） and configurable logic block （CLB） of FPGA automatically, exhaustively and repeatedly. Fault cells of FPGA can be positioned automatically by the proposed approach. As a result, test efficiency and reliability can be enhanced without manual work.展开更多
In a conventional direct torque control(CDTC) of the induction motor drive, the electromagnetic torque and the stator flux are characterized by high ripples. In order to reduce the undesired ripples, several methods a...In a conventional direct torque control(CDTC) of the induction motor drive, the electromagnetic torque and the stator flux are characterized by high ripples. In order to reduce the undesired ripples, several methods are used in the literature. Nevertheless,these methods increase the algorithm complexity and dependency on the machine parameters such as the space vector modulation(SVM). The fuzzy logic control method is utilized in this work to decrease these ripples. Moreover, to eliminate the mechanical sensor the extended kalman filter(EKF) is used, in order to reduce the cost of the system and the rate of maintenance. Furthermore, in the domain of controlling the real-time induction motor drives, two principal digital devices are used such as the hardware(FPGA) and the digital signal processing(DSP). The latter is a software solution featured by a sequential processing that increases the execution time. However, the FPGA is featured by a high processing speed because of its parallel processing. Therefore, using the FPGA it is possible to implement complex algorithms with low execution time and to enhance the control bandwidth. The large bandwidth is the key issue to increase the system performances. This paper presents the interest of utilizing the FPGAs to implement complex control algorithms of electrical systems in real time. The suggested sensorless direct torque control using the fuzzy logic(DTFC) of an induction motor is successfully designed and implemented on an FPGA Virtex 5 using xilinx system generator. The simulation and implementation results show proposed approach s performances in terms of ripples, stator current harmonic waves, execution time, and short design time.展开更多
文摘An intelligent fuzzy logic inference pipeline for the control of a dc-dc buck-boost converter was designed and built using a semi-custom VLSI chip. The fuzzy linguistics describing the switching topologies of the converter was mapped into a look-up table that was synthesized into a set of Boolean equations. A VLSI chip–a field programmable gate array (FPGA) was used to implement the Boolean equations. Features include the size of RAM chip independent of number of rules in the knowledge base, on-chip fuzzification and defuzzification, faster response with speeds over giga fuzzy logic inferences per sec (FLIPS), and an inexpensive VLSI chip. The key application areas are: 1) on-chip integrated controllers;and 2) on-chip co-integration for entire system of sensors, circuits, controllers, and detectors for building complete instrument systems.
基金Supported by the Commission of Science Technology and Industry for National Defense and the National Natural Science Foundation of China (No. 90307011)
文摘Programmable Logic Array (PLA) is an important building circuit of VLSI chips and some of the FPGA architectures have evolved from the basic PLA architectures. In this letter, a dynamic and static mixed PLA with single-phased clock is presented. Combining both dynamic and static design style rather than introducing additional interface-buffers overcomes the racing problem, thereby saves the chip area. Besides inheriting the advantages of dynamic circuit-low power dissipation and compact structure, this approach also provides high-speed operation.
基金supported by the National Natural Science Foundation of China(No.62174150)the Natural Science Foundation of Jiangsu Province,China(Nos.BK20211040 and BK20211041)。
文摘This paper proposes a kind of programmable logic element(PLE)based on Sense-Switch pFLASH technology.By programming Sense-Switch pFLASH,all three-bit look-up table(LUT3)functions,partial four-bit look-up table(LUT4)functions,latch functions,and d flip flop(DFF)with enable and reset functions can be realized.Because PLE uses a choice of operational logic(COOL)approach for the operation of logic functions,it allows any logic circuit to be implemented at any ratio of combinatorial logic to register.This intrinsic property makes it close to the basic application specific integrated circuit(ASIC)cell in terms of fine granularity,thus allowing ASIC-like cell-based mappers to apply all their optimization potential.By measuring Sense-Switch pFLASH and PLE circuits,the results show that the“on”state driving current of the Sense-Switch pFLASH is about 245.52μA,and that the“off”state leakage current is about 0.1 pA.The programmable function of PLE works normally.The delay of the typical combinatorial logic operation AND3 is 0.69 ns,and the delay of the sequential logic operation DFF is 0.65 ns,both of which meet the requirements of the design technical index.
基金Project supported by the National Natural Science Foundation of China, and subsidized by K. C. Edu cation Foundation.
文摘Programmable logic array (PLA) is a popular structure for realizing arbitrary combinational networks. Easy test generation (ETG) PLA, a kind of PLA design with the property of easy test generation, is s PLA design with added product terms and/or outputs such that tests are easy to generate, even no effort on test generation and fault simulation is necessary. This paper attempts to further clarify the concept of ETG circuits and extends the concepts of pseudo-nonconcurrency and separation to reduce the hardware overhead, based on a unified singlefault model. Experimental results show that the hardware overhead is generally less than 5%, which is considered to be the lowest cost for testable PLA designs.
基金the National Science Foundation of China(Nos.60934007 and 61074060)the Postdoctoral Science Foundation of China(No.20090460627)+2 种基金the Postdoctoral Scientific Program of Shanghai (No.10R21414600)the Specialized Research Fund for the Doctoral Program of Higher Education (No.20070248004)the China Postdoctoral Science Foundation Special Support(No.201003272)
文摘High performance computer is often required by model predictive control(MPC) systems due to the heavy online computation burden.To extend MPC to more application cases with low-cost computation facilities, the implementation of MPC controller on field programmable gate array(FPGA) system is studied.For the dynamic matrix control(DMC) algorithm,the main design idea and the implemental strategy of DMC controller are introduced based on a FPGA’s embedded system.The performance tests show that both the computation efficiency and the accuracy of the proposed controller can be satisfied due to the parallel computing capability of FPGA.
基金Supported by National Natural Science Foundation of China(No.61271149)National High Technology Research and Development Program of China(No.2012AA-012301)National Science and Technology Major Project of China(No.2013ZX03006004)
文摘Field Programmable Gate Array(FPGA) is an efficient reconfigurable integrated circuit platform and has become a core signal processing microchip device of digital systems over the last decade. With the rapid development of semiconductor technology, the performance and system integration of FPGA devices have been significantly progressed, and at the same time new challenges arise. The design of FPGA architecture is required to evolve to meet these challenges, while also taking advantage of ever increased microchip density. This survey reviews the recent development of advanced FPGA architectures, including improvement of the programming technologies, logic blocks, interconnects, and embedded resources. Moreover, some important emerging design issues of FPGA architectures, such as novel memory based FPGAs and 3D FPGAs, are also presented to provide an outlook for future FPGA development.
文摘Introduces the characteristic of FPGA,motion estimation and full search block matching arithmetic,analyses collectivity configuration of basic working flow in ME and discusses in detall the control,computing and test part of ME chip implementation.
基金supported by Key Techniques of FPGA Architecture under Grant No.9140A08010106QT9201the support from UESTC Youth Funds
文摘Field programmable gate arrays （FPGAs） have wide and extensive applications in many areas. Due to programmable feature of FPGAs, faults of FPGAs can be easily tolerated if fault sites can be located. A hardware/software （HW/SW） co-verification technique for FPGA test is proposed in this paper. Taking advantage of flexibility and observability of software in conjunction with high-speed simulation of hardware, this technique is capable of testing each input/output block （IOB） and configurable logic block （CLB） of FPGA automatically, exhaustively and repeatedly. Fault cells of FPGA can be positioned automatically by the proposed approach. As a result, test efficiency and reliability can be enhanced without manual work.
文摘In a conventional direct torque control(CDTC) of the induction motor drive, the electromagnetic torque and the stator flux are characterized by high ripples. In order to reduce the undesired ripples, several methods are used in the literature. Nevertheless,these methods increase the algorithm complexity and dependency on the machine parameters such as the space vector modulation(SVM). The fuzzy logic control method is utilized in this work to decrease these ripples. Moreover, to eliminate the mechanical sensor the extended kalman filter(EKF) is used, in order to reduce the cost of the system and the rate of maintenance. Furthermore, in the domain of controlling the real-time induction motor drives, two principal digital devices are used such as the hardware(FPGA) and the digital signal processing(DSP). The latter is a software solution featured by a sequential processing that increases the execution time. However, the FPGA is featured by a high processing speed because of its parallel processing. Therefore, using the FPGA it is possible to implement complex algorithms with low execution time and to enhance the control bandwidth. The large bandwidth is the key issue to increase the system performances. This paper presents the interest of utilizing the FPGAs to implement complex control algorithms of electrical systems in real time. The suggested sensorless direct torque control using the fuzzy logic(DTFC) of an induction motor is successfully designed and implemented on an FPGA Virtex 5 using xilinx system generator. The simulation and implementation results show proposed approach s performances in terms of ripples, stator current harmonic waves, execution time, and short design time.
