This paper presents an RF receiver of zero-Intermediate Frequency(IF) architecture for Cognitive Radio(CR) communication systems.Zero-IF architecture reduce the image reject filter and IF filter,so it is excellent in ...This paper presents an RF receiver of zero-Intermediate Frequency(IF) architecture for Cognitive Radio(CR) communication systems.Zero-IF architecture reduce the image reject filter and IF filter,so it is excellent in low cost,compact volume,and low power dissipation.The receiver employs three digital attenuator and a high gain,high linearity low noise amplifier to achieve wide dynamic range of 70 dB and high receiving sensitivity of-81 dBm.A fully balanced I/Q demodulator and a differential Local Oscillator(LO) chips are used to minimize the negative effects caused by second-order distortion and LO leakage.In order to select an 8 MHz-channel from 14 continuous ones located in UHF band(694-806 MHz) accurately,approach of channel selectivity circuits is proposed.The RF receiver has been designed,fabricated,and test.The measured result shows that the noise figure is 3.4 dB,and the error vector magnitude is 7.5% when the input power is-81 dBm.展开更多
A fully integrated dual-band RF receiver with a low-IF architecture is designed and implemented for GPS-L 1 and Compass-Bl in a 55-nm CMOS process. The receiver incorporates two independent IF channels with 2 or 4 MHz...A fully integrated dual-band RF receiver with a low-IF architecture is designed and implemented for GPS-L 1 and Compass-Bl in a 55-nm CMOS process. The receiver incorporates two independent IF channels with 2 or 4 MHz bandwidth to receive dual-band signals around 1.57 GHz respectively. By implementing a flexible frequency plan, the RF front-end and frequency synthesizer are shared for the dual-band operation to save power consumption and chip area, as well as avoiding LO crosstalk. A digital automatic gain control （AGC） loop is utilized to improve the receiver＇s robustness by optimizing the conversion gain of the analog-to-digital converter （ADC）. While drawing about 20 mA per channel from a 1.2 V supply, this RF receiver achieves a minimum noise figure （NF） of about 1.8 dB, an image rejection （IMR） of more than 35 dB, a maximum voltage gain of about 122 dB, a gain dynamic range of 82 dB, and an maximum input-referred 1 dB compression point of about -36.5 dBm with an active die area of 1.5 × 1.4 mm2 for the whole chip.展开更多
One of the most important electron density diagnostics, microwave reflectometry, has been developed on many large and medium nuclear fusion devices in recent years . Not only the electron density profiles with high te...One of the most important electron density diagnostics, microwave reflectometry, has been developed on many large and medium nuclear fusion devices in recent years . Not only the electron density profiles with high temporal and spatial resolutions, but also the profiles of plasma rotation and turbulence can be obtained with this diagnostic system.展开更多
This article presents an L1 band low noise integrated global positioning system （GPS） receiver chip using 0.18 μm CMOS technology. Dual-conversion with a low-IF architecture was used for this GPS receiver. The rece...This article presents an L1 band low noise integrated global positioning system （GPS） receiver chip using 0.18 μm CMOS technology. Dual-conversion with a low-IF architecture was used for this GPS receiver. The receiver is composed of low noise amplifier （LNA）, down-conversion mixers, band pass filter, received signal strength indicator, variable gain amplifier, programmable gain amplifier, ADC, PLL frequency synthesizer and other key blocks. The receiver achieves a maximum gain of 105 dB and noise figure less than 6 dB. The variable gain amplifier （VGA） and programmable gain amplifier （PGA） provide gain control dynamic range over 50 dB. The receiver consumes less than 160 mW from a 1.8 V supply while occupying a 2.9 mm2 chip area including the ESD I/O pads.展开更多
This paper presents a high linearity downconverter implemented in a 0.18μm CMOS process for long term evolution（LTE） receivers without a surface acoustic wave（SAW） filter.The proposed downconverter is composed of...This paper presents a high linearity downconverter implemented in a 0.18μm CMOS process for long term evolution（LTE） receivers without a surface acoustic wave（SAW） filter.The proposed downconverter is composed of a transconductance（Gm） stage,a passive mixer,a current buffer,a transimpedance（TIA） stage,and a DC-offset cancellation（DCOC） loop.The current buffer is utilized to provide very low load impedance for the passive mixer at high frequencies and reduce the output voltage swing induced by out-of-band blockers.This technique improves the input referred third-order intercept point（IIP3） and second-order intercept point（IIP2） of the down-converter by 4.5 dB and 11 dB,respectively.The measured results show that the proposed downconverter achieves a voltage conversion gain of 29.5 dB,double sideband noise figure of 12.7 dB,out-of-band IIP3 of 13 dBm and IIP2 of more than 62 dBm.展开更多
基金Supported by the National High-Tech Project (No. 2009AA011801)National Natural Science Foundation of China (No. 60621002)
文摘This paper presents an RF receiver of zero-Intermediate Frequency(IF) architecture for Cognitive Radio(CR) communication systems.Zero-IF architecture reduce the image reject filter and IF filter,so it is excellent in low cost,compact volume,and low power dissipation.The receiver employs three digital attenuator and a high gain,high linearity low noise amplifier to achieve wide dynamic range of 70 dB and high receiving sensitivity of-81 dBm.A fully balanced I/Q demodulator and a differential Local Oscillator(LO) chips are used to minimize the negative effects caused by second-order distortion and LO leakage.In order to select an 8 MHz-channel from 14 continuous ones located in UHF band(694-806 MHz) accurately,approach of channel selectivity circuits is proposed.The RF receiver has been designed,fabricated,and test.The measured result shows that the noise figure is 3.4 dB,and the error vector magnitude is 7.5% when the input power is-81 dBm.
基金Project supported by the Science and Technology Innovation Project for the Postgraduates of National University of Defense Technology
文摘A fully integrated dual-band RF receiver with a low-IF architecture is designed and implemented for GPS-L 1 and Compass-Bl in a 55-nm CMOS process. The receiver incorporates two independent IF channels with 2 or 4 MHz bandwidth to receive dual-band signals around 1.57 GHz respectively. By implementing a flexible frequency plan, the RF front-end and frequency synthesizer are shared for the dual-band operation to save power consumption and chip area, as well as avoiding LO crosstalk. A digital automatic gain control （AGC） loop is utilized to improve the receiver＇s robustness by optimizing the conversion gain of the analog-to-digital converter （ADC）. While drawing about 20 mA per channel from a 1.2 V supply, this RF receiver achieves a minimum noise figure （NF） of about 1.8 dB, an image rejection （IMR） of more than 35 dB, a maximum voltage gain of about 122 dB, a gain dynamic range of 82 dB, and an maximum input-referred 1 dB compression point of about -36.5 dBm with an active die area of 1.5 × 1.4 mm2 for the whole chip.
文摘One of the most important electron density diagnostics, microwave reflectometry, has been developed on many large and medium nuclear fusion devices in recent years . Not only the electron density profiles with high temporal and spatial resolutions, but also the profiles of plasma rotation and turbulence can be obtained with this diagnostic system.
基金supported by the National Natural Science Foundation of China (60976029)
文摘This article presents an L1 band low noise integrated global positioning system （GPS） receiver chip using 0.18 μm CMOS technology. Dual-conversion with a low-IF architecture was used for this GPS receiver. The receiver is composed of low noise amplifier （LNA）, down-conversion mixers, band pass filter, received signal strength indicator, variable gain amplifier, programmable gain amplifier, ADC, PLL frequency synthesizer and other key blocks. The receiver achieves a maximum gain of 105 dB and noise figure less than 6 dB. The variable gain amplifier （VGA） and programmable gain amplifier （PGA） provide gain control dynamic range over 50 dB. The receiver consumes less than 160 mW from a 1.8 V supply while occupying a 2.9 mm2 chip area including the ESD I/O pads.
基金supported by the National High Technology Research and Development Program of China(No.2009AA011608)the National Major Science and Technology Projects Program of China(No.2009ZX03002-004-02)
文摘This paper presents a high linearity downconverter implemented in a 0.18μm CMOS process for long term evolution（LTE） receivers without a surface acoustic wave（SAW） filter.The proposed downconverter is composed of a transconductance（Gm） stage,a passive mixer,a current buffer,a transimpedance（TIA） stage,and a DC-offset cancellation（DCOC） loop.The current buffer is utilized to provide very low load impedance for the passive mixer at high frequencies and reduce the output voltage swing induced by out-of-band blockers.This technique improves the input referred third-order intercept point（IIP3） and second-order intercept point（IIP2） of the down-converter by 4.5 dB and 11 dB,respectively.The measured results show that the proposed downconverter achieves a voltage conversion gain of 29.5 dB,double sideband noise figure of 12.7 dB,out-of-band IIP3 of 13 dBm and IIP2 of more than 62 dBm.
