Convolutional neural networks(CNNs) exhibit excellent performance in the areas of image recognition and object detection, which can enhance the intelligence level of spacecraft. However, in aerospace, energetic partic...Convolutional neural networks(CNNs) exhibit excellent performance in the areas of image recognition and object detection, which can enhance the intelligence level of spacecraft. However, in aerospace, energetic particles, such as heavy ions, protons, and alpha particles, can induce single event effects(SEEs) that lead CNNs to malfunction and can significantly impact the reliability of a CNN system. In this paper, the MNIST CNN system was constructed based on a 28 nm systemon-chip(SoC), and then an alpha particle irradiation experiment and fault injection were applied to evaluate the SEE of the CNN system. Various types of soft errors in the CNN system have been detected, and the SEE cross sections have been calculated. Furthermore, the mechanisms behind some soft errors have been explained. This research will provide technical support for the design of radiation-resistant artificial intelligence chips.展开更多
The propagation of single-event effects(SEEs)on a Xilinx Zynq-7000 system on chip(SoC)was inves-tigated using heavy-ion microbeam radiation.The irradia-tion results reveal several functional blocks’sensitivity locati...The propagation of single-event effects(SEEs)on a Xilinx Zynq-7000 system on chip(SoC)was inves-tigated using heavy-ion microbeam radiation.The irradia-tion results reveal several functional blocks’sensitivity locations and cross sections,for instance,the arithmetic logic unit,register,D-cache,and peripheral,while irradi-ating the on-chip memory(OCM)region.Moreover,event tree analysis was executed based on the obtained microbeam irradiation results.This study quantitatively assesses the probabilities of SEE propagation from the OCM to other blocks in the SoC.展开更多
In this paper, the design and verification process of an automobile-engine-fan control system on chip （SoC） are introduced. The SoC system, SHU-MV08, reuses four new intellectual property （IP） cores and the design...In this paper, the design and verification process of an automobile-engine-fan control system on chip （SoC） are introduced. The SoC system, SHU-MV08, reuses four new intellectual property （IP） cores and the design flow is accomplished with 0.35 btm chartered CMOS technology. Some special functions of IP cores, the detailed integration scheme of four IP cores, and the verification method of the entire SoC are presented. To settle the verification problems brought by analog IP cores, NanoSim based chip-level mixed-signal verification method is introduced. The verification time is greatly reduced and the first tape-out achieves success which proves the validity of our design.展开更多
The network on chip（NoC）is used as a solution for the communication problems in a complex system on chip（SoC）design.To further enhance performances,the NoC architectures,a high level modeling and an evaluation met...The network on chip（NoC）is used as a solution for the communication problems in a complex system on chip（SoC）design.To further enhance performances,the NoC architectures,a high level modeling and an evaluation method based on OPNET are proposed to analyze their performances on different injection rates and traffic patterns.Simulation results for general NoC in terms of the average latency and the throughput are analyzed and used as a guideline to make appropriate choices for a given application.Finally,a MPEG4 decoder is mapped on different NoC architectures.Results prove the effectiveness of the evaluation method.展开更多
Networks-on-chip （NoC）, a new system on chip （SoC） paradigm, has become a great focus of research by many groups during the last few years. Among all the NoC architectures that have been proposed until now, 2D-Mes...Networks-on-chip （NoC）, a new system on chip （SoC） paradigm, has become a great focus of research by many groups during the last few years. Among all the NoC architectures that have been proposed until now, 2D-Mesh has proved to be the best architecture for implementation due to its regular and simple interconnection structure. In this paper, we propose a new interconnect architecture called 2D-diagonal mesh （2DDgl-Mesh） for on-chip communication. The 2DDglMesh is almost similar to traditional 2D-Mesh in aspects of cost, area, and implementation, but it can outperform the later in delay. The both architectures are compared by using NS-2 （a network simulator） and CINS1M （a component based interconnection simulator） under the same traffic models and parametric conditions. The results of comparison show that under the proposed architecture, the packets can almost always be routed to their destinations in less time. In addition, our archi- tecture can sometimes perform better than 2D-Mesh in drop ratio for special fixed traffic models.展开更多
This paper presents the tire pressure monitoring system (TPMS) by using the system on chip (SoC) mixed signals with the help of Bluetooth transmission and in advantage of low power consumption design. This is to monit...This paper presents the tire pressure monitoring system (TPMS) by using the system on chip (SoC) mixed signals with the help of Bluetooth transmission and in advantage of low power consumption design. This is to monitor the variations in temperature and pressure of the vehicle’s tire, and the TPMS system is involved. It improves the driver’s safety by automatically detecting the tire pressure and temperature and then warning signal is sent to driver to take a measure, which prevents from accident. The proposed system of tire pressure monitoring system using SoC increases the speed of indication time to the driver by using mixed signals. The inflation of the tire can be avoided by preventing from high temperature and high pressure. Limitation of temperature and pressure in the previous system is also elongated i.e. temperature from 40℃ to 125℃ and pressure from 0 to 750 Kpa. Sensors, wireless communication (Bluetooth dongle) and SoC unit are used to design the low power TPMS. Quantitative results are taken and the analogy between temperature and pressure is also verified. The tested results proved by need of the practical system. Signal conditioning voltage and SoC unit is the trace for low power design TPMS. Finally, the performance of the system is tested and executed by using proteus software given as a real time application.展开更多
With further increase of the number of on-chip device, the bus structure has not met the requirements. In order to make better communication between each part, the chip designers need to explore a new structure to sol...With further increase of the number of on-chip device, the bus structure has not met the requirements. In order to make better communication between each part, the chip designers need to explore a new structure to solve the interconnection of on-chip device. The paper proposes a network-on-chip dynamic and adaptive algorithm which selects NoC platform with 2-dimension mesh as the carrier, incorporates communication energy consumption and delay into unified cost function and uses ant colony optimization to realize NOC map facing energy consumption and delay. The experiment indicates that compared with random map, single objective optimization can separately saves （30% - 47 %） and （ 20% - 39%） in communication energy consumption and execution time compared with random map, and joint objective optimization can further excavate the potential of time dimension in mapping scheme dominated by the energy.展开更多
As the increasing desire for more compact,portable devices outpaces Moore’s law,innovation in packaging and system design has played a significant role in the continued miniaturization of electronic systems.Integrati...As the increasing desire for more compact,portable devices outpaces Moore’s law,innovation in packaging and system design has played a significant role in the continued miniaturization of electronic systems.Integrating more active and passive components into the package itself,as the case for system-on-package(SoP),has shown very promising results in overall size reduction and increased performance of electronic systems.With this ability to shrink electrical systems comes the many challenges of sustaining,let alone improving,reliability and performance.The fundamental signal,power,and thermal integrity issues are discussed in detail,along with published techniques from around the industry to mitigate these issues in SoP applications.展开更多
Increasing the life span and efficiency of Multiprocessor System on Chip(MPSoC)by reducing power and energy utilization has become a critical chip design challenge for multiprocessor systems.With the advancement of te...Increasing the life span and efficiency of Multiprocessor System on Chip(MPSoC)by reducing power and energy utilization has become a critical chip design challenge for multiprocessor systems.With the advancement of technology,the performance management of central processing unit(CPU)is changing.Power densities and thermal effects are quickly increasing in multi-core embedded technologies due to shrinking of chip size.When energy consumption reaches a threshold that creates a delay in complementary metal oxide semiconductor(CMOS)circuits and reduces the speed by 10%–15%because excessive on-chip temperature shortens the chip’s life cycle.In this paper,we address the scheduling&energy utilization problem by introducing and evaluating an optimal energy-aware earliest deadline first scheduling(EA-EDF)based technique formultiprocessor environments with task migration that enhances the performance and efficiency in multiprocessor systemon-chip while lowering energy and power consumption.The selection of core andmigration of tasks prevents the system from reaching itsmaximumenergy utilization while effectively using the dynamic power management(DPM)policy.Increase in the execution of tasks the temperature and utilization factor(u_(i))on-chip increases that dissipate more power.The proposed approach migrates such tasks to the core that produces less heat and consumes less power by distributing the load on other cores to lower the temperature and optimizes the duration of idle and sleep times across multiple CPUs.The performance of the EA-EDF algorithm was evaluated by an extensive set of experiments,where excellent results were reported when compared to other current techniques,the efficacy of the proposed methodology reduces the power and energy consumption by 4.3%–4.7%on a utilization of 6%,36%&46%at 520&624 MHz operating frequency when particularly in comparison to other energy-aware methods for MPSoCs.Tasks are running and accurately scheduled to make an energy-efficient processor by controlling and managing the thermal effects on-chip and optimizing the energy consumption of MPSoCs.展开更多
Aims to provide the block architecture of CoStar3400 DSP that is a high performance, low power and scalable VLIW DSP core, it efficiently deployed a variable-length execution set (VLES) execution model which utilizes ...Aims to provide the block architecture of CoStar3400 DSP that is a high performance, low power and scalable VLIW DSP core, it efficiently deployed a variable-length execution set (VLES) execution model which utilizes the maximum parallelism by allowing multiple address generations and data arithmetic logic units to execute multiple instructions in a single clock cycle. The scalability was provided mainly in using more or less number of functional units according to the intended application. Low power support was added by careful architectural design techniques such as fine-grain clock gating and activation of only the required number of control signals at each stage of the pipeline. The said features of the core make it a suitable candidate for many SoC configurations, especially for compute intensive applications such as wire-line and wireless communications, including infrastructure and subscriber communications. The embedded system designers can efficiently use the scalability and VLIW features of the core by scaling the number of execution units according to specific needs of the application to effectively reduce the power consumption, chip area and time to market the intended final product.展开更多
To collect neural activity data from awake, behaving freely animals, we develop miniaturized implantable recording system by the modem chip：Programmable System on Chip （PSoC） and through chronic electrodes in the c...To collect neural activity data from awake, behaving freely animals, we develop miniaturized implantable recording system by the modem chip：Programmable System on Chip （PSoC） and through chronic electrodes in the cortex. With PSoC family member CY8C29466,the system completed operational and instrument amplifiers, filters, timers, AD convertors, and serial communication, etc. The signal processing was dealt with virtual instrument technology. All of these factors can significantly affect the price and development cycle of the project. The result showed that the system was able to record and analyze neural extrocellular discharge generated by neurons continuously for a week or more. This is very useful for the interdisciplinary research of neuroscience and information engineering technique. The circuits and architecture of the devices can be adapted for neurobiology and research with other small animals.展开更多
MV10 is an MCU which consists of PWM, ADC,CAN and some other function blocks. It is designed for car body＇s control. Advanced peripheral bus （APB） is a low speed AMBA bus connecting low-power peripherals. This pape...MV10 is an MCU which consists of PWM, ADC,CAN and some other function blocks. It is designed for car body＇s control. Advanced peripheral bus （APB） is a low speed AMBA bus connecting low-power peripherals. This paper presents an implementation of APB interface for MV10 MCU. After that, MV10 can be integrated into any AMBA system on chips （SoCs） easily. We have built a multi-core system with ABMA to verify this design, In this system ARM9 is a main processor mounted on AHB and MV10 acts as a low-power and low-speed slaver on APB. Before building this system, some operations are encapsulated into a task with dedicated ID. MV10 works as a co-processor with ARM by acquiring task ID from ARM. The result of simulation indicates that MCU can work well as expected. Based on our design, MV10 can be mounted on any AMBA system from now on.展开更多
The growing complexity of System on Chip （SOC） requres a system level specicanon and design approach. High-level languages such as C＋＋/SystemC can play multiple roles in system design as target languages. There ar...The growing complexity of System on Chip （SOC） requres a system level specicanon and design approach. High-level languages such as C＋＋/SystemC can play multiple roles in system design as target languages. There are many practical problems in the application of object-oriented methods for this goal. Based on the analysis of traditional and system-level design methodology, a new object-oriented SOC design methodology with object-oriented design patterns is proposed, which emphasizes high-level design and verification. Aiming at the final goal of developing design patterns specific to SOC design, the reuse of design patterns in SOC systems and the capability of new SOC design patterns are discussed. With the illustration of some concrete examples of SOC design patterns, the application of object-oriented design methodology in the SOC design process is presented.展开更多
Minimizing the energy consumption to increase the life span and performance of multiprocessor system on chip(MPSoC)has become an integral chip design issue for multiprocessor systems.The performance measurement of com...Minimizing the energy consumption to increase the life span and performance of multiprocessor system on chip(MPSoC)has become an integral chip design issue for multiprocessor systems.The performance measurement of computational systems is changing with the advancement in technology.Due to shrinking and smaller chip size power densities onchip are increasing rapidly that increasing chip temperature in multi-core embedded technologies.The operating speed of the device decreases when power consumption reaches a threshold that causes a delay in complementary metal oxide semiconductor(CMOS)circuits because high on-chip temperature adversely affects the life span of the chip.In this paper an energy-aware dynamic power management technique based on energy aware earliest deadline first(EA-EDF)scheduling is proposed for improving the performance and reliability by reducing energy and power consumption in the system on chip(SOC).Dynamic power management(DPM)enables MPSOC to reduce power and energy consumption by adopting a suitable core configuration for task migration.Task migration avoids peak temperature values in the multicore system.High utilization factor(ui)on central processing unit(CPU)core consumes more energy and increases the temperature on-chip.Our technique switches the core bymigrating such task to a core that has less temperature and is in a low power state.The proposed EA-EDF scheduling technique migrates load on different cores to attain stability in temperature among multiple cores of the CPU and optimized the duration of the idle and sleep periods to enable the low-temperature core.The effectiveness of the EA-EDF approach reduces the utilization and energy consumption compared to other existing methods and works.The simulation results show the improvement in performance by optimizing 4.8%on u_(i) 9%,16%,23%and 25%at 520 MHz operating frequency as compared to other energy-aware techniques for MPSoCs when the least number of tasks is in running state and can schedule more tasks to make an energy-efficient processor by controlling and managing the energy consumption of MPSoC.展开更多
为了在自行车转向或变道时,实现无需左右回头观察即可了解后方路况,设计了一套便于骑行者感知车后具体情况的自行车后视系统.该系统可分为车尾探测装置与终端反应手套,主要由USB摄像头与执行模块构成,并采用了you only look once(YOLO)v...为了在自行车转向或变道时,实现无需左右回头观察即可了解后方路况,设计了一套便于骑行者感知车后具体情况的自行车后视系统.该系统可分为车尾探测装置与终端反应手套,主要由USB摄像头与执行模块构成,并采用了you only look once(YOLO)v4目标检测算法.通过在自行车车尾安装检测设备,与骑手的特制手套进行无线通信,从而传递车后方探测到的有关安全状况的紧急信息.实验结果表明:该系统能够对后方的行进车辆进行多目标检测及警告优先级目标,并在足够的安全距离内识别率较高.展开更多
基金Project supported by the National Natural Science Foundation of China(Grant No.12305303)the Natural Science Foundation of Hunan Province of China(Grant Nos.2023JJ40520,2021JJ40444,and 2019JJ30019)+3 种基金the Research Foundation of Education Bureau of Hunan Province of China(Grant No.20A430)the Science and Technology Innovation Program of Hunan Province(Grant No.2020RC3054)the Natural Science Basic Research Plan in the Shaanxi Province of China(Grant No.2023-JC-QN-0015)the Doctoral Research Fund of University of South China。
文摘Convolutional neural networks(CNNs) exhibit excellent performance in the areas of image recognition and object detection, which can enhance the intelligence level of spacecraft. However, in aerospace, energetic particles, such as heavy ions, protons, and alpha particles, can induce single event effects(SEEs) that lead CNNs to malfunction and can significantly impact the reliability of a CNN system. In this paper, the MNIST CNN system was constructed based on a 28 nm systemon-chip(SoC), and then an alpha particle irradiation experiment and fault injection were applied to evaluate the SEE of the CNN system. Various types of soft errors in the CNN system have been detected, and the SEE cross sections have been calculated. Furthermore, the mechanisms behind some soft errors have been explained. This research will provide technical support for the design of radiation-resistant artificial intelligence chips.
基金This work was supported by the National Natural Science Foundation of China(Nos.11575138,11835006,11690040,11690043,and 11705216)the Innovation Center of Radiation Application(No.KFZC2019050321)the China Scholarships Council program(No.201906280343).
文摘The propagation of single-event effects(SEEs)on a Xilinx Zynq-7000 system on chip(SoC)was inves-tigated using heavy-ion microbeam radiation.The irradia-tion results reveal several functional blocks’sensitivity locations and cross sections,for instance,the arithmetic logic unit,register,D-cache,and peripheral,while irradi-ating the on-chip memory(OCM)region.Moreover,event tree analysis was executed based on the obtained microbeam irradiation results.This study quantitatively assesses the probabilities of SEE propagation from the OCM to other blocks in the SoC.
基金Project supported by the IC Special Foundation of Shanghai Municipal Commission of Science and Technology (Grant No.09706201300)the Shanghai Municipal Commission of Economic and Information (Grant No.090344)the Shanghai High-Tech Industrialization of New Energy Vehicles (Grant No.09625029),and the Graduate Innovation Foundation of Shanghai University
文摘In this paper, the design and verification process of an automobile-engine-fan control system on chip （SoC） are introduced. The SoC system, SHU-MV08, reuses four new intellectual property （IP） cores and the design flow is accomplished with 0.35 btm chartered CMOS technology. Some special functions of IP cores, the detailed integration scheme of four IP cores, and the verification method of the entire SoC are presented. To settle the verification problems brought by analog IP cores, NanoSim based chip-level mixed-signal verification method is introduced. The verification time is greatly reduced and the first tape-out achieves success which proves the validity of our design.
基金Supported by the Natural Science Foundation of China(61076019)the China Postdoctoral Science Foundation(20100481134)+1 种基金the Natural Science Foundation of Jiangsu Province(BK2008387)the Graduate Student Innovation Foundation of Jiangsu Province(CX07B-105z)~~
文摘The network on chip（NoC）is used as a solution for the communication problems in a complex system on chip（SoC）design.To further enhance performances,the NoC architectures,a high level modeling and an evaluation method based on OPNET are proposed to analyze their performances on different injection rates and traffic patterns.Simulation results for general NoC in terms of the average latency and the throughput are analyzed and used as a guideline to make appropriate choices for a given application.Finally,a MPEG4 decoder is mapped on different NoC architectures.Results prove the effectiveness of the evaluation method.
基金supported by the National Natural Science Foundation of China under Grant No.60425413
文摘Networks-on-chip （NoC）, a new system on chip （SoC） paradigm, has become a great focus of research by many groups during the last few years. Among all the NoC architectures that have been proposed until now, 2D-Mesh has proved to be the best architecture for implementation due to its regular and simple interconnection structure. In this paper, we propose a new interconnect architecture called 2D-diagonal mesh （2DDgl-Mesh） for on-chip communication. The 2DDglMesh is almost similar to traditional 2D-Mesh in aspects of cost, area, and implementation, but it can outperform the later in delay. The both architectures are compared by using NS-2 （a network simulator） and CINS1M （a component based interconnection simulator） under the same traffic models and parametric conditions. The results of comparison show that under the proposed architecture, the packets can almost always be routed to their destinations in less time. In addition, our archi- tecture can sometimes perform better than 2D-Mesh in drop ratio for special fixed traffic models.
文摘This paper presents the tire pressure monitoring system (TPMS) by using the system on chip (SoC) mixed signals with the help of Bluetooth transmission and in advantage of low power consumption design. This is to monitor the variations in temperature and pressure of the vehicle’s tire, and the TPMS system is involved. It improves the driver’s safety by automatically detecting the tire pressure and temperature and then warning signal is sent to driver to take a measure, which prevents from accident. The proposed system of tire pressure monitoring system using SoC increases the speed of indication time to the driver by using mixed signals. The inflation of the tire can be avoided by preventing from high temperature and high pressure. Limitation of temperature and pressure in the previous system is also elongated i.e. temperature from 40℃ to 125℃ and pressure from 0 to 750 Kpa. Sensors, wireless communication (Bluetooth dongle) and SoC unit are used to design the low power TPMS. Quantitative results are taken and the analogy between temperature and pressure is also verified. The tested results proved by need of the practical system. Signal conditioning voltage and SoC unit is the trace for low power design TPMS. Finally, the performance of the system is tested and executed by using proteus software given as a real time application.
文摘With further increase of the number of on-chip device, the bus structure has not met the requirements. In order to make better communication between each part, the chip designers need to explore a new structure to solve the interconnection of on-chip device. The paper proposes a network-on-chip dynamic and adaptive algorithm which selects NoC platform with 2-dimension mesh as the carrier, incorporates communication energy consumption and delay into unified cost function and uses ant colony optimization to realize NOC map facing energy consumption and delay. The experiment indicates that compared with random map, single objective optimization can separately saves （30% - 47 %） and （ 20% - 39%） in communication energy consumption and execution time compared with random map, and joint objective optimization can further excavate the potential of time dimension in mapping scheme dominated by the energy.
文摘As the increasing desire for more compact,portable devices outpaces Moore’s law,innovation in packaging and system design has played a significant role in the continued miniaturization of electronic systems.Integrating more active and passive components into the package itself,as the case for system-on-package(SoP),has shown very promising results in overall size reduction and increased performance of electronic systems.With this ability to shrink electrical systems comes the many challenges of sustaining,let alone improving,reliability and performance.The fundamental signal,power,and thermal integrity issues are discussed in detail,along with published techniques from around the industry to mitigate these issues in SoP applications.
文摘Increasing the life span and efficiency of Multiprocessor System on Chip(MPSoC)by reducing power and energy utilization has become a critical chip design challenge for multiprocessor systems.With the advancement of technology,the performance management of central processing unit(CPU)is changing.Power densities and thermal effects are quickly increasing in multi-core embedded technologies due to shrinking of chip size.When energy consumption reaches a threshold that creates a delay in complementary metal oxide semiconductor(CMOS)circuits and reduces the speed by 10%–15%because excessive on-chip temperature shortens the chip’s life cycle.In this paper,we address the scheduling&energy utilization problem by introducing and evaluating an optimal energy-aware earliest deadline first scheduling(EA-EDF)based technique formultiprocessor environments with task migration that enhances the performance and efficiency in multiprocessor systemon-chip while lowering energy and power consumption.The selection of core andmigration of tasks prevents the system from reaching itsmaximumenergy utilization while effectively using the dynamic power management(DPM)policy.Increase in the execution of tasks the temperature and utilization factor(u_(i))on-chip increases that dissipate more power.The proposed approach migrates such tasks to the core that produces less heat and consumes less power by distributing the load on other cores to lower the temperature and optimizes the duration of idle and sleep times across multiple CPUs.The performance of the EA-EDF algorithm was evaluated by an extensive set of experiments,where excellent results were reported when compared to other current techniques,the efficacy of the proposed methodology reduces the power and energy consumption by 4.3%–4.7%on a utilization of 6%,36%&46%at 520&624 MHz operating frequency when particularly in comparison to other energy-aware methods for MPSoCs.Tasks are running and accurately scheduled to make an energy-efficient processor by controlling and managing the thermal effects on-chip and optimizing the energy consumption of MPSoCs.
基金the National Natural Science Foundation of China(Grant No.60425413)COMSATS Institute of Information Technology, Pakistan
文摘Aims to provide the block architecture of CoStar3400 DSP that is a high performance, low power and scalable VLIW DSP core, it efficiently deployed a variable-length execution set (VLES) execution model which utilizes the maximum parallelism by allowing multiple address generations and data arithmetic logic units to execute multiple instructions in a single clock cycle. The scalability was provided mainly in using more or less number of functional units according to the intended application. Low power support was added by careful architectural design techniques such as fine-grain clock gating and activation of only the required number of control signals at each stage of the pipeline. The said features of the core make it a suitable candidate for many SoC configurations, especially for compute intensive applications such as wire-line and wireless communications, including infrastructure and subscriber communications. The embedded system designers can efficiently use the scalability and VLIW features of the core by scaling the number of execution units according to specific needs of the application to effectively reduce the power consumption, chip area and time to market the intended final product.
基金Shandong Province Nature Science FoundationGrant number:Y2007C02+1 种基金Science Development PlanGrant number:2006GG3204006
文摘To collect neural activity data from awake, behaving freely animals, we develop miniaturized implantable recording system by the modem chip：Programmable System on Chip （PSoC） and through chronic electrodes in the cortex. With PSoC family member CY8C29466,the system completed operational and instrument amplifiers, filters, timers, AD convertors, and serial communication, etc. The signal processing was dealt with virtual instrument technology. All of these factors can significantly affect the price and development cycle of the project. The result showed that the system was able to record and analyze neural extrocellular discharge generated by neurons continuously for a week or more. This is very useful for the interdisciplinary research of neuroscience and information engineering technique. The circuits and architecture of the devices can be adapted for neurobiology and research with other small animals.
基金supported by the IC Special Foundation of Science and Technology Commission of Shanghai Municipality(Grant No.09706201300)the Shanghai Municipal Commission of Economic and Information(Grant No.090344)the Shanghai High-Technology Industrialization of New Energy Vehicles(Grant No.09625029)
文摘MV10 is an MCU which consists of PWM, ADC,CAN and some other function blocks. It is designed for car body＇s control. Advanced peripheral bus （APB） is a low speed AMBA bus connecting low-power peripherals. This paper presents an implementation of APB interface for MV10 MCU. After that, MV10 can be integrated into any AMBA system on chips （SoCs） easily. We have built a multi-core system with ABMA to verify this design, In this system ARM9 is a main processor mounted on AHB and MV10 acts as a low-power and low-speed slaver on APB. Before building this system, some operations are encapsulated into a task with dedicated ID. MV10 works as a co-processor with ARM by acquiring task ID from ARM. The result of simulation indicates that MCU can work well as expected. Based on our design, MV10 can be mounted on any AMBA system from now on.
文摘The growing complexity of System on Chip （SOC） requres a system level specicanon and design approach. High-level languages such as C＋＋/SystemC can play multiple roles in system design as target languages. There are many practical problems in the application of object-oriented methods for this goal. Based on the analysis of traditional and system-level design methodology, a new object-oriented SOC design methodology with object-oriented design patterns is proposed, which emphasizes high-level design and verification. Aiming at the final goal of developing design patterns specific to SOC design, the reuse of design patterns in SOC systems and the capability of new SOC design patterns are discussed. With the illustration of some concrete examples of SOC design patterns, the application of object-oriented design methodology in the SOC design process is presented.
文摘Minimizing the energy consumption to increase the life span and performance of multiprocessor system on chip(MPSoC)has become an integral chip design issue for multiprocessor systems.The performance measurement of computational systems is changing with the advancement in technology.Due to shrinking and smaller chip size power densities onchip are increasing rapidly that increasing chip temperature in multi-core embedded technologies.The operating speed of the device decreases when power consumption reaches a threshold that causes a delay in complementary metal oxide semiconductor(CMOS)circuits because high on-chip temperature adversely affects the life span of the chip.In this paper an energy-aware dynamic power management technique based on energy aware earliest deadline first(EA-EDF)scheduling is proposed for improving the performance and reliability by reducing energy and power consumption in the system on chip(SOC).Dynamic power management(DPM)enables MPSOC to reduce power and energy consumption by adopting a suitable core configuration for task migration.Task migration avoids peak temperature values in the multicore system.High utilization factor(ui)on central processing unit(CPU)core consumes more energy and increases the temperature on-chip.Our technique switches the core bymigrating such task to a core that has less temperature and is in a low power state.The proposed EA-EDF scheduling technique migrates load on different cores to attain stability in temperature among multiple cores of the CPU and optimized the duration of the idle and sleep periods to enable the low-temperature core.The effectiveness of the EA-EDF approach reduces the utilization and energy consumption compared to other existing methods and works.The simulation results show the improvement in performance by optimizing 4.8%on u_(i) 9%,16%,23%and 25%at 520 MHz operating frequency as compared to other energy-aware techniques for MPSoCs when the least number of tasks is in running state and can schedule more tasks to make an energy-efficient processor by controlling and managing the energy consumption of MPSoC.
文摘为了在自行车转向或变道时,实现无需左右回头观察即可了解后方路况,设计了一套便于骑行者感知车后具体情况的自行车后视系统.该系统可分为车尾探测装置与终端反应手套,主要由USB摄像头与执行模块构成,并采用了you only look once(YOLO)v4目标检测算法.通过在自行车车尾安装检测设备,与骑手的特制手套进行无线通信,从而传递车后方探测到的有关安全状况的紧急信息.实验结果表明:该系统能够对后方的行进车辆进行多目标检测及警告优先级目标,并在足够的安全距离内识别率较高.
