This paper presents a novel adaptive-bandwidth charge pump PLL with low jitter and a wide tuning range. With an adaptive bandwidth,the proposed PLL can scale its loop dynamics proportional to the output frequency and ...This paper presents a novel adaptive-bandwidth charge pump PLL with low jitter and a wide tuning range. With an adaptive bandwidth,the proposed PLL can scale its loop dynamics proportional to the output frequency and maintain optimal performance over its entire output range. In order to improve the jitter performance of the PLL,a matching tech- nique is employed in the charge pump,and a voltage-to-voltage converter is used to achieve a low gain VCO. The experimental chip was fabricated in a 0. 35μm CMOS process. The measured results show that the PLL has perfect jitter performance within its operating range from 200MHz to 1.1GHz.展开更多
In this article, we consider a class of kernel quantile estimators which is the linear combi- nation of order statistics. This class of kernel quantile estimators can be regarded as an extension of some existing estim...In this article, we consider a class of kernel quantile estimators which is the linear combi- nation of order statistics. This class of kernel quantile estimators can be regarded as an extension of some existing estimators. The exact mean square error expression for this class of estimators will be provided when data are uniformly distributed. The implementation of these estimators depends mostly on the bandwidth selection. We then develop an adaptive method for bandwidth selection based on the intersection confidence intervals （ICI） principle. Monte Carlo studies demonstrate that our proposed approach is comparatively remarkable. We illustrate our method with a real data set.展开更多
A novel particle filter bandwidth adaption for kernel particle filter （BAKPF） is proposed. Selection of the kernel bandwidth is a critical issue in kernel density estimation （KDE）. The plug-in method is adopted to...A novel particle filter bandwidth adaption for kernel particle filter （BAKPF） is proposed. Selection of the kernel bandwidth is a critical issue in kernel density estimation （KDE）. The plug-in method is adopted to get the global fixed bandwidth by optimizing the asymptotic mean integrated squared error （AMISE） firstly. Then, particle-driven bandwidth selection is invoked in the KDE. To get a more effective allocation of the particles, the KDE with adap- tive bandwidth in the BAKPF is used to approximate the posterior probability density function （PDF） by moving particles toward the posterior. A closed-form expression of the true distribution is given. The simulation results show that the proposed BAKPF performs better than the standard particle filter （PF）, unscented particle filter （UPF） and the kernel particle filter （KPF） both in efficiency and estimation precision.展开更多
The merits of compressed air energy storage(CAES)include large power generation capacity,long service life,and environmental safety.When a CAES plant is switched to the grid-connected mode and participates in grid reg...The merits of compressed air energy storage(CAES)include large power generation capacity,long service life,and environmental safety.When a CAES plant is switched to the grid-connected mode and participates in grid regulation,using the traditional control mode with low accuracy can result in excess grid-connected impulse current and junction voltage.This occurs because the CAES output voltage does not match the frequency,amplitude,and phase of the power grid voltage.Therefore,an adaptive linear active disturbance-rejection control(A-LADRC)strategy was proposed.Based on the LADRC strategy,which is more accurate than the traditional proportional integral controller,the proposed controller is enhanced to allow adaptive adjustment of bandwidth parameters,resulting in improved accuracy and response speed.The problem of large impulse current when CAES is switched to the grid-connected mode is addressed,and the frequency fluctuation is reduced.Finally,the effectiveness of the proposed strategy in reducing the impact of CAES on the grid connection was verified using a hardware-in-the-loop simulation platform.The influence of the k value in the adaptive-adjustment formula on the A-LADRC was analyzed through simulation.The anti-interference performance of the control was verified by increasing and decreasing the load during the presynchronization process.展开更多
The self biased Phase Locked Loop (PLL) has become a default choice for clock generation in many microprocessors. In today’s scenario, the processor cores are made to operate at rapidly varying combinations of clock ...The self biased Phase Locked Loop (PLL) has become a default choice for clock generation in many microprocessors. In today’s scenario, the processor cores are made to operate at rapidly varying combinations of clock frequencies and very low supply voltages. Though the traditional self biased PLL is still being widely used with hardly any modification, it is becoming imperative to take a relook at the design aspects of these PLLs with respect to their jitter performance. This paper presents a systematic simulation study of designing the self biased PLL with the goal of reducing jitter. It further shows that if the self biased PLL is adapted into a dual loop scheme in a systematic manner, a significant jitter improvement can be obtained. Detailed simulations carried out in 0.18 μm CMOS technology indicate a reduction of 56% or more in jitter for the systematically designed dual loop scheme in comparison to the jitter reduced traditional self biased PLL.展开更多
文摘This paper presents a novel adaptive-bandwidth charge pump PLL with low jitter and a wide tuning range. With an adaptive bandwidth,the proposed PLL can scale its loop dynamics proportional to the output frequency and maintain optimal performance over its entire output range. In order to improve the jitter performance of the PLL,a matching tech- nique is employed in the charge pump,and a voltage-to-voltage converter is used to achieve a low gain VCO. The experimental chip was fabricated in a 0. 35μm CMOS process. The measured results show that the PLL has perfect jitter performance within its operating range from 200MHz to 1.1GHz.
基金Supported by Fundamental Research Funds for the Central Universities and the Research Funds of Renmin University of China(Grant Nos.10XNL018,10XNK025)National Natural Science Foundation of China(Grant No.11271368)+3 种基金Beijing Planning Office of Philosophy and Social Science(Grant No.12JGB051)China Statistical Research Project(Grant No.2011LZ031)Project of Ministry of Education supported by the Specialized Research Fund for the Doctoral Program of Higher Education of China(Grant No.20130004110007)the Key Program of National Philosophy and Social Science Foundation Grant(No.13AZD064)
文摘In this article, we consider a class of kernel quantile estimators which is the linear combi- nation of order statistics. This class of kernel quantile estimators can be regarded as an extension of some existing estimators. The exact mean square error expression for this class of estimators will be provided when data are uniformly distributed. The implementation of these estimators depends mostly on the bandwidth selection. We then develop an adaptive method for bandwidth selection based on the intersection confidence intervals （ICI） principle. Monte Carlo studies demonstrate that our proposed approach is comparatively remarkable. We illustrate our method with a real data set.
基金supported by the National Natural Science Foundation of China (60736043 60805012)the Fundamental Research Funds for the Central Universities (K50510020032)
文摘A novel particle filter bandwidth adaption for kernel particle filter （BAKPF） is proposed. Selection of the kernel bandwidth is a critical issue in kernel density estimation （KDE）. The plug-in method is adopted to get the global fixed bandwidth by optimizing the asymptotic mean integrated squared error （AMISE） firstly. Then, particle-driven bandwidth selection is invoked in the KDE. To get a more effective allocation of the particles, the KDE with adap- tive bandwidth in the BAKPF is used to approximate the posterior probability density function （PDF） by moving particles toward the posterior. A closed-form expression of the true distribution is given. The simulation results show that the proposed BAKPF performs better than the standard particle filter （PF）, unscented particle filter （UPF） and the kernel particle filter （KPF） both in efficiency and estimation precision.
基金supported by National Natural Science Foundation of China(Project No.52077079).
文摘The merits of compressed air energy storage(CAES)include large power generation capacity,long service life,and environmental safety.When a CAES plant is switched to the grid-connected mode and participates in grid regulation,using the traditional control mode with low accuracy can result in excess grid-connected impulse current and junction voltage.This occurs because the CAES output voltage does not match the frequency,amplitude,and phase of the power grid voltage.Therefore,an adaptive linear active disturbance-rejection control(A-LADRC)strategy was proposed.Based on the LADRC strategy,which is more accurate than the traditional proportional integral controller,the proposed controller is enhanced to allow adaptive adjustment of bandwidth parameters,resulting in improved accuracy and response speed.The problem of large impulse current when CAES is switched to the grid-connected mode is addressed,and the frequency fluctuation is reduced.Finally,the effectiveness of the proposed strategy in reducing the impact of CAES on the grid connection was verified using a hardware-in-the-loop simulation platform.The influence of the k value in the adaptive-adjustment formula on the A-LADRC was analyzed through simulation.The anti-interference performance of the control was verified by increasing and decreasing the load during the presynchronization process.
文摘The self biased Phase Locked Loop (PLL) has become a default choice for clock generation in many microprocessors. In today’s scenario, the processor cores are made to operate at rapidly varying combinations of clock frequencies and very low supply voltages. Though the traditional self biased PLL is still being widely used with hardly any modification, it is becoming imperative to take a relook at the design aspects of these PLLs with respect to their jitter performance. This paper presents a systematic simulation study of designing the self biased PLL with the goal of reducing jitter. It further shows that if the self biased PLL is adapted into a dual loop scheme in a systematic manner, a significant jitter improvement can be obtained. Detailed simulations carried out in 0.18 μm CMOS technology indicate a reduction of 56% or more in jitter for the systematically designed dual loop scheme in comparison to the jitter reduced traditional self biased PLL.
