A novel Time-Interleaved Analog-to-Digital Converter (TIADC) digital background calibration for the mismatches of offsets, gain errors, and timing skews based on split-ADC is proposed. Firstly, the split-ADC channels ...A novel Time-Interleaved Analog-to-Digital Converter (TIADC) digital background calibration for the mismatches of offsets, gain errors, and timing skews based on split-ADC is proposed. Firstly, the split-ADC channels in present TIADC architecture are designed to convert input signal at two different channel sampling rates so that redundant channel to facilitate pair permutation is avoided. Secondly, a high-order compensation scheme for correction of timing skew error is employed for effective calibration to preserve high-resolution when input frequency is high. Numerical simulation performed by MATLAB for a 14-bit TIADC based on 7 split-ADC channels shows that Signal-to-Noise and Distortion Ratio (SNDR) and Spurious Free Dynamic Range (SFDR) of the TIADC achieve 86.2 dBc and 106 dBc respectively after calibration with normalized input frequency near Nyquist frequency.展开更多
A fractional-N frequency synthesizer for 433/868MHz SRD applications is implemented in a 0.3μm CMOS process. A wide-band VCO and an AFC are used to cover the desired bands. A 3bit third order sigma-delta modulator is...A fractional-N frequency synthesizer for 433/868MHz SRD applications is implemented in a 0.3μm CMOS process. A wide-band VCO and an AFC are used to cover the desired bands. A 3bit third order sigma-delta modulator is adopted to reduce the out-band phase noise. The measurements show a VCO tuning range from 1.31 to 1.88GHz with AFC working correctly,an out-band phase noise of -139dBc/Hz at 3MHz offset frequency, and a fractional spur of less than - 60dBc. The chip area is 1.5mm × 1.2mm and the total current dissipation including LO buffers is 19mA from a single 3.0V supply voltage.展开更多
An improved adaptive frequency calibration（AFC） has been employed to implement a fast lock phaselocked loop based frequency synthesizer in a 0.18μm CMOS process.The AFC can work in two modes：the frequency calibrat...An improved adaptive frequency calibration（AFC） has been employed to implement a fast lock phaselocked loop based frequency synthesizer in a 0.18μm CMOS process.The AFC can work in two modes：the frequency calibration mode and the store/load mode.In the frequency calibration mode,a novel frequency-detector is used to reduce the frequency calibration time to 16 us typically.In the store/load mode,the AFC makes the voltage-controlled oscillator（VCO） return to the calibrated frequency in about 1μs by loading the calibration result stored after the frequency calibration.The experimental results show that the VCO tuning frequency range is about 620-920 MHz and the in-band phase noise within the loop bandwidth of 10 kHz is-82 dBc/Hz.The lock time is about 20μs in frequency calibration mode and about 5 us in store/load mode.The synthesizer consumes 12 mA from a single 1.8 V supply voltage when steady.展开更多
A wide range fractional-N frequency synthesizer in 0.18μm RF CMOS technology is implemented. A switched-capacitors bank LC-tank VCO and an adaptive frequency calibration technique are used to expand the frequency ran...A wide range fractional-N frequency synthesizer in 0.18μm RF CMOS technology is implemented. A switched-capacitors bank LC-tank VCO and an adaptive frequency calibration technique are used to expand the frequency range.A 16-bit third-order sigma-delta modulator with dither is used to randomize the fractional spur. The active area is 0.6 mm;.The experimental results show the proposed frequency synthesizer consumes 4.3 raA from a single 1.8 V supply voltage except for buffers.The frequency range is 1.44-2.11 GHz and the frequency resolution is less than 0.4 kHz.The phase noise is -94 dBc/Hz @ 100 kHz and -121 dBc/Hz @ 1 MHz at the output of the prescaler with a loop bandwidth of approximately 120 kHz.The performance meets the requirements for the multi-band and multi-mode transceiver applications.展开更多
A fully integrated phase-locked loop（PLL） is presented for a single quadrature output frequency of 3.96 GHz.The proposed PLL can be applied to mode-1 MB-OFDM UWB hopping carrier generation.An adaptive frequency cali...A fully integrated phase-locked loop（PLL） is presented for a single quadrature output frequency of 3.96 GHz.The proposed PLL can be applied to mode-1 MB-OFDM UWB hopping carrier generation.An adaptive frequency calibration loop is incorporated into the PLL.The capacitance area in the loop filter is largely reduced through a capacitor multiplier.Implemented in a CMOS process, this PLL draws 13.0 mA current from a single 1.2 V supply while occupying 0.55 mm2 die area.Measurement results show that the PLL achieves a phase noise of-70 dBc/Hz at 10 kHz offset and-113 dBc/Hz at 1 MHz offset.The integrated RMS jitter from 1 kHz to 10 MHz is 2.2 ps.The reference spur level is less than-68 dBc.展开更多
基金Supported by the National Natural Science Foundation of China (No. 61076026)
文摘A novel Time-Interleaved Analog-to-Digital Converter (TIADC) digital background calibration for the mismatches of offsets, gain errors, and timing skews based on split-ADC is proposed. Firstly, the split-ADC channels in present TIADC architecture are designed to convert input signal at two different channel sampling rates so that redundant channel to facilitate pair permutation is avoided. Secondly, a high-order compensation scheme for correction of timing skew error is employed for effective calibration to preserve high-resolution when input frequency is high. Numerical simulation performed by MATLAB for a 14-bit TIADC based on 7 split-ADC channels shows that Signal-to-Noise and Distortion Ratio (SNDR) and Spurious Free Dynamic Range (SFDR) of the TIADC achieve 86.2 dBc and 106 dBc respectively after calibration with normalized input frequency near Nyquist frequency.
文摘A fractional-N frequency synthesizer for 433/868MHz SRD applications is implemented in a 0.3μm CMOS process. A wide-band VCO and an AFC are used to cover the desired bands. A 3bit third order sigma-delta modulator is adopted to reduce the out-band phase noise. The measurements show a VCO tuning range from 1.31 to 1.88GHz with AFC working correctly,an out-band phase noise of -139dBc/Hz at 3MHz offset frequency, and a fractional spur of less than - 60dBc. The chip area is 1.5mm × 1.2mm and the total current dissipation including LO buffers is 19mA from a single 3.0V supply voltage.
基金Project supported by the National High Technology Research and Development Program of China(No.2007AA01Z2a8).
文摘An improved adaptive frequency calibration（AFC） has been employed to implement a fast lock phaselocked loop based frequency synthesizer in a 0.18μm CMOS process.The AFC can work in two modes：the frequency calibration mode and the store/load mode.In the frequency calibration mode,a novel frequency-detector is used to reduce the frequency calibration time to 16 us typically.In the store/load mode,the AFC makes the voltage-controlled oscillator（VCO） return to the calibrated frequency in about 1μs by loading the calibration result stored after the frequency calibration.The experimental results show that the VCO tuning frequency range is about 620-920 MHz and the in-band phase noise within the loop bandwidth of 10 kHz is-82 dBc/Hz.The lock time is about 20μs in frequency calibration mode and about 5 us in store/load mode.The synthesizer consumes 12 mA from a single 1.8 V supply voltage when steady.
文摘A wide range fractional-N frequency synthesizer in 0.18μm RF CMOS technology is implemented. A switched-capacitors bank LC-tank VCO and an adaptive frequency calibration technique are used to expand the frequency range.A 16-bit third-order sigma-delta modulator with dither is used to randomize the fractional spur. The active area is 0.6 mm;.The experimental results show the proposed frequency synthesizer consumes 4.3 raA from a single 1.8 V supply voltage except for buffers.The frequency range is 1.44-2.11 GHz and the frequency resolution is less than 0.4 kHz.The phase noise is -94 dBc/Hz @ 100 kHz and -121 dBc/Hz @ 1 MHz at the output of the prescaler with a loop bandwidth of approximately 120 kHz.The performance meets the requirements for the multi-band and multi-mode transceiver applications.
基金supported by the National Natural Science Foundation of China(No.60606009)
文摘A fully integrated phase-locked loop（PLL） is presented for a single quadrature output frequency of 3.96 GHz.The proposed PLL can be applied to mode-1 MB-OFDM UWB hopping carrier generation.An adaptive frequency calibration loop is incorporated into the PLL.The capacitance area in the loop filter is largely reduced through a capacitor multiplier.Implemented in a CMOS process, this PLL draws 13.0 mA current from a single 1.2 V supply while occupying 0.55 mm2 die area.Measurement results show that the PLL achieves a phase noise of-70 dBc/Hz at 10 kHz offset and-113 dBc/Hz at 1 MHz offset.The integrated RMS jitter from 1 kHz to 10 MHz is 2.2 ps.The reference spur level is less than-68 dBc.
