Using quantum algorithms to solve various problems has attracted widespread attention with the development of quantum computing.Researchers are particularly interested in using the acceleration properties of quantum a...Using quantum algorithms to solve various problems has attracted widespread attention with the development of quantum computing.Researchers are particularly interested in using the acceleration properties of quantum algorithms to solve NP-complete problems.This paper focuses on the well-known NP-complete problem of finding the minimum dominating set in undirected graphs.To expedite the search process,a quantum algorithm employing Grover’s search is proposed.However,a challenge arises from the unknown number of solutions for the minimum dominating set,rendering direct usage of original Grover’s search impossible.Thus,a swap test method is introduced to ascertain the number of iterations required.The oracle,diffusion operators,and swap test are designed with achievable quantum gates.The query complexity is O(1.414^(n))and the space complexity is O(n).To validate the proposed approach,qiskit software package is employed to simulate the quantum circuit,yielding the anticipated results.展开更多
With the development of semiconductor technology,the size of transistors continues to shrink.In complex radiation environments in aerospace and other fields,small-sized circuits are more prone to soft error(SE).Curren...With the development of semiconductor technology,the size of transistors continues to shrink.In complex radiation environments in aerospace and other fields,small-sized circuits are more prone to soft error(SE).Currently,single-node upset(SNU),double-node upset(DNU)and triple-node upset(TNU)caused by SE are relatively common.TNU’s solution is not yet fully mature.A novel and low-cost TNU self-recoverable latch(named NLCTNURL)was designed which is resistant to harsh radiation effects.When analyzing circuit resiliency,a double-exponential current source is used to simulate the flipping behavior of a node’s stored value when an error occurs.Simulation results show that the latch has full TNU self-recovery.A comparative analysis was conducted on seven latches related to TNU.Besides,a comprehensive index combining delay,power,area and self-recovery—DPAN index was proposed,and all eight types of latches from the perspectives of delay,power,area,and DPAN index were analyzed and compared.The simulation results show that compared with the latches LCTNURL and TNURL which can also achieve TNU self-recoverable,NLCTNURL is reduced by 68.23%and 57.46%respectively from the perspective of delay.From the perspective of power,NLCTNURL is reduced by 72.84%and 74.19%,respectively.From the area perspective,NLCTNURL is reduced by about 28.57%and 53.13%,respectively.From the DPAN index perspective,NLCTNURL is reduced by about 93.12%and 97.31%.The simulation results show that the delay and power stability of the circuit are very high no matter in different temperatures or operating voltages.展开更多
Neo-Chinese style is popular nowadays and it is wildly used in rural landscape,with only few theories.Under the background of rural revitalization,this paper discussed practice types and design features of neo-Chinese...Neo-Chinese style is popular nowadays and it is wildly used in rural landscape,with only few theories.Under the background of rural revitalization,this paper discussed practice types and design features of neo-Chinese style in rural landscape.Some typical and famous villages of Ningbo,Quzhou and Lishui cities in Zhejiang Province were chosen as cases in this paper.It is committed to providing some theories,inheriting rural culture and promoting rural revitalization.展开更多
Based on two modified Rsslor hyperchaotic systems, which are derived from the chaotic Rsslor system by introducing a state feedback controller, this paper proposes a new switched Rsslor hyperchaotic system. The ...Based on two modified Rsslor hyperchaotic systems, which are derived from the chaotic Rsslor system by introducing a state feedback controller, this paper proposes a new switched Rsslor hyperchaotic system. The switched system contains two different hyperchaotic systems and can change its behaviour continuously from one to another via a switching function. On the other hand, it presents a systematic method for designing the circuit of realizing the proposed hyperchaotic system. In this design, circuit state equations are written in normalized dimensionless form by rescaling the time variable. Furthermore, an analogous circuit is designed by using the proposed method and built for verifying the new hyperchaos and the design method. Experimental results show a good agreement between numerical simulations and experimental results.展开更多
First the research is conducted on the design of the two-phase sinusoidal power clock gen- erator in this paper. Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks—Clock...First the research is conducted on the design of the two-phase sinusoidal power clock gen- erator in this paper. Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks—Clocked Transmission Gate Adiabatic Logic (CTGAL) circuit is presented. This circuit makes use of the clocked transmission gates to sample the input signals, then the output loads are charged and discharged in a fully adiabatic manner by using bootstrapped N-Channel Metal Oxide Semiconductor (NMOS) and Complementary Metal Oxide Semiconductor (CMOS) latch structure. Finally, with the parameters of Taiwan Semiconductor Manufacturing Company (TSMC) 0.25μm CMOS device, the transient energy consumption of CTGAL, Bootstrap Charge-Recovery Logic (BCRL) and Pass-transistor Adiabatic Logic (PAL) including their clock generators is simulated. The simula-tion result indicates that CTGAL circuit has the characteristic of remarkably low energy consumption.展开更多
The paper discusses general expressions of the clock signal and the next state equations containing the clock signal for flip-flops, and based on it, a unified theory for designing and analyzing both synchronous and a...The paper discusses general expressions of the clock signal and the next state equations containing the clock signal for flip-flops, and based on it, a unified theory for designing and analyzing both synchronous and asynchronous sequential circuits is proposed. The theory is proved effective by practical examples.展开更多
Categories of earth-sheltered buildings were summarized, and it was proposed that landscape features of earth-sheltered buildings were demonstrated mainly as "ecological, landscape-like and systematic". Land...Categories of earth-sheltered buildings were summarized, and it was proposed that landscape features of earth-sheltered buildings were demonstrated mainly as "ecological, landscape-like and systematic". Landscape elements such as entrance, road, water and greening were believed as major means of showing landscape features of earth-sheltered buildings. Entrance landscape design of such buildings was analyzed from the perspectives of plane-type, slope-type and step-type forms. Road design for these buildings should respect natural terrains so as to connect spaces and organize traffic routes reasonably. Waterscape design should take both landscape effects and loading capacity of roof into consideration so as to meet water-loving psychology of the public, virtual and real approaches should be combined to create waterscapes. Greening design of earth-sheltered buildings was explored from the perspectives of roof greening and vertical greening to improve the green coverage rate and show favorable ecological effects.展开更多
This paper describes the design and implementation of a hydraulic circuit design system using case-based reasoning (CBR) paradigm from AI community The domain of hydraulic circuit design and case-based reasoning are b...This paper describes the design and implementation of a hydraulic circuit design system using case-based reasoning (CBR) paradigm from AI community The domain of hydraulic circuit design and case-based reasoning are briefly reviewed Then a proposed methodology in compuer-aided circuit design and dynamic leaning with the use of CBR is described Finally an application example is selected to illustrate the ussfulness of applying CBR in hydraulic circuit design with leaming.展开更多
The basic indexes of all-optical integrated photonic circuits include high-density integration,ultrafast response and ultralow energy consumption.Traditional methods mainly adopt conventional micro/nano-structures.The...The basic indexes of all-optical integrated photonic circuits include high-density integration,ultrafast response and ultralow energy consumption.Traditional methods mainly adopt conventional micro/nano-structures.The overall size of the circuit is large,usually reaches hundreds of microns.Besides,it is difficult to balance the ultrafast response and ultra-low energy consumption problem,and the crosstalk between two traditional devices is difficult to overcome.Here,we propose and experimentally demonstrate an approach based on inverse design method to realize a high-density,ultrafast and ultra-low energy consumption integrated photonic circuit with two all-optical switches controlling the input states of an all-optical XOR logic gate.The feature size of the whole circuit is only 2.5μm×7μm,and that of a single device is 2μm×2μm.The distance between two adjacent devices is as small as 1.5μm,within wavelength magnitude scale.Theoretical response time of the circuit is 150 fs,and the threshold energy is within 10 fJ/bit.We have also considered the crosstalk problem.The circuit also realizes a function of identifying two-digit logic signal results.Our work provides a new idea for the design of ultrafast,ultra-low energy consumption all-optical devices and the implementation of high-density photonic integrated circuits.展开更多
In view of the limitations of a Rn-Gn model in the low frequency range and the defects of an En-In model in common use now, this paper builds a complete En-In model according to the theory of random harmonic. The para...In view of the limitations of a Rn-Gn model in the low frequency range and the defects of an En-In model in common use now, this paper builds a complete En-In model according to the theory of random harmonic. The parameters for the low-noise design such as the equivalent input noisy voltage Ens, the optimum source impedance Zsopt and the minimum noise figure Fmin can be calculated accurately by using this En-In model because it considers the coherence between the noise sources fully. Moreover, this paper points out that it will cause the maximum 30% miscalculation when neglecting the effects of the correlation coefficient 7. Using the series-series circuits as an example, this paper discusses the methods for the En-In noise analysis of electronic circuits preliminarily and demonstrates its correctness through the comparison between the simulated and measured results of the minimum noise figure Fmin of a single current series negative feedback circuit.展开更多
A multi-valued logic system is a promising alternative to traditional binary logic because it can reduce the complexity,power consumption, and area of circuit implementation. This article briefly summarizes the develo...A multi-valued logic system is a promising alternative to traditional binary logic because it can reduce the complexity,power consumption, and area of circuit implementation. This article briefly summarizes the development of ternary logic and its advantages in digital logic circuits. The schemes, characteristics, and application of ternary logic circuits based on CMOS, CNTFET, memristor, and other devices and processes are reviewed in this paper, providing some reference for the further research and development of ternary logic circuits.展开更多
Choosing the right characteristic parameter is the key to fault diagnosis in analog circuit. The featureevaluation and extraction methods based on neural network are presented. Parameter evaluation of circuit features...Choosing the right characteristic parameter is the key to fault diagnosis in analog circuit. The featureevaluation and extraction methods based on neural network are presented. Parameter evaluation of circuit features is realized by training results from neural network; the superior nonlinear mapping capability is competent for extracting fault features which are normalized and compressed subsequently. The complex classification problem on fault pattern recognition in analog circuit is transferred into feature processing stage by feature extraction based on neural network effectively, which improves the diagnosis efficiency. A fault diagnosis illustration validated this method.展开更多
A double photodiode(PD) constructed by p^+/N-well junction and N-well/p-sub junction was designed and fabricated in a UMC 0.18-lm CMOS process. Based on the device structure and mechanism of double PD, a novel small-s...A double photodiode(PD) constructed by p^+/N-well junction and N-well/p-sub junction was designed and fabricated in a UMC 0.18-lm CMOS process. Based on the device structure and mechanism of double PD, a novel small-signal equivalent circuit model considering the carrier transit effect and the parasitic RC time constant was presented. By this model with complete electronic components, the double PD can be incorporated in a commercial circuit simulator. The component values were extracted by fitting the measured S-parameters using simulated annealing algorithm, and a good agreement between the measurement and the simulation results was achieved.展开更多
Based on analyzing significance of controlling clock in design of low power sequential circuits, this paper proposes a technique that the gating signal is derived from the master latch in a flip-flop to make the deriv...Based on analyzing significance of controlling clock in design of low power sequential circuits, this paper proposes a technique that the gating signal is derived from the master latch in a flip-flop to make the derived clock having no glitch and no skew. The design of a decimal counter with half-frequency division shows that by using the synchronous derived clock the counter has lower power dissipation as well as simpler combinational logic. Computer simulation shows 20% power saving.展开更多
Realizing the layouts of analog/mixed-signal(AMS)integrated circuits(ICs)is a complicated task due to the high design flexibility and sensitive circuit performance.Compared with the advancements of digital IC layout a...Realizing the layouts of analog/mixed-signal(AMS)integrated circuits(ICs)is a complicated task due to the high design flexibility and sensitive circuit performance.Compared with the advancements of digital IC layout automation,analog IC layout design is still heavily manual,which leads to a more time-consuming and error-prone process.In recent years,significant progress has been made in automated analog layout design with emerging of several open-source frameworks.This paper firstly reviews the existing state-of-the art AMS layout synthesis frameworks with focus on the different approaches and their individual challenges.We then present recent research trends and opportunities in the field.Finally,we summaries the paper with open questions and future directions for fully-automating the analog IC layout.展开更多
In this paper, the synchronization of the fractional-order generalized augmented Lu¨ system is investigated. Based on the predictor–corrector method, we obtain phase portraits, bifurcation diagrams, Lyapunov exp...In this paper, the synchronization of the fractional-order generalized augmented Lu¨ system is investigated. Based on the predictor–corrector method, we obtain phase portraits, bifurcation diagrams, Lyapunov exponent spectra, and Poincare′maps of the fractional-order system and find that a four-wing chaotic attractor exists in the system when the system parameters change within certain ranges. Further, by varying the system parameters, rich dynamical behaviors occur in the2.7-order system. According to the stability theory of a fractional-order linear system, and adopting the linearization by feedback method, we have designed a nonlinear feedback controller in our theoretical analysis to implement the synchronization of the drive system with the response system. In addition, the synchronization is also shown by an electronic circuit implementation for the 2.7-order system. The obtained experiment results accord with the theoretical analyses,which further demonstrate the feasibility and effectiveness of the proposed synchronization scheme.展开更多
基金Project supported by the National Natural Science Foundation of China(Grant No.62101600)the Science Foundation of China University of Petroleum,Beijing(Grant No.2462021YJRC008)the State Key Laboratory of Cryptology(Grant No.MMKFKT202109).
文摘Using quantum algorithms to solve various problems has attracted widespread attention with the development of quantum computing.Researchers are particularly interested in using the acceleration properties of quantum algorithms to solve NP-complete problems.This paper focuses on the well-known NP-complete problem of finding the minimum dominating set in undirected graphs.To expedite the search process,a quantum algorithm employing Grover’s search is proposed.However,a challenge arises from the unknown number of solutions for the minimum dominating set,rendering direct usage of original Grover’s search impossible.Thus,a swap test method is introduced to ascertain the number of iterations required.The oracle,diffusion operators,and swap test are designed with achievable quantum gates.The query complexity is O(1.414^(n))and the space complexity is O(n).To validate the proposed approach,qiskit software package is employed to simulate the quantum circuit,yielding the anticipated results.
基金The Open Project Program of the Shanxi Key Laboratory of Advanced Semiconductor Optoelectronic Devices and Integrated Systems(2023SZKF17)the University Synergy Innovation Program of Anhui Province(GXXT-2022-080)。
文摘With the development of semiconductor technology,the size of transistors continues to shrink.In complex radiation environments in aerospace and other fields,small-sized circuits are more prone to soft error(SE).Currently,single-node upset(SNU),double-node upset(DNU)and triple-node upset(TNU)caused by SE are relatively common.TNU’s solution is not yet fully mature.A novel and low-cost TNU self-recoverable latch(named NLCTNURL)was designed which is resistant to harsh radiation effects.When analyzing circuit resiliency,a double-exponential current source is used to simulate the flipping behavior of a node’s stored value when an error occurs.Simulation results show that the latch has full TNU self-recovery.A comparative analysis was conducted on seven latches related to TNU.Besides,a comprehensive index combining delay,power,area and self-recovery—DPAN index was proposed,and all eight types of latches from the perspectives of delay,power,area,and DPAN index were analyzed and compared.The simulation results show that compared with the latches LCTNURL and TNURL which can also achieve TNU self-recoverable,NLCTNURL is reduced by 68.23%and 57.46%respectively from the perspective of delay.From the perspective of power,NLCTNURL is reduced by 72.84%and 74.19%,respectively.From the area perspective,NLCTNURL is reduced by about 28.57%and 53.13%,respectively.From the DPAN index perspective,NLCTNURL is reduced by about 93.12%and 97.31%.The simulation results show that the delay and power stability of the circuit are very high no matter in different temperatures or operating voltages.
基金the General Science Project of Zhejiang Education Department,China(Y202045325).
文摘Neo-Chinese style is popular nowadays and it is wildly used in rural landscape,with only few theories.Under the background of rural revitalization,this paper discussed practice types and design features of neo-Chinese style in rural landscape.Some typical and famous villages of Ningbo,Quzhou and Lishui cities in Zhejiang Province were chosen as cases in this paper.It is committed to providing some theories,inheriting rural culture and promoting rural revitalization.
基金Project supported by the Natural Science Foundation of Zhejiang Province, China (Grant No Y105175)the Science Investigation Foundation of Hangzhou Dianzi University, China (Grant No KYS051505010)
文摘Based on two modified Rsslor hyperchaotic systems, which are derived from the chaotic Rsslor system by introducing a state feedback controller, this paper proposes a new switched Rsslor hyperchaotic system. The switched system contains two different hyperchaotic systems and can change its behaviour continuously from one to another via a switching function. On the other hand, it presents a systematic method for designing the circuit of realizing the proposed hyperchaotic system. In this design, circuit state equations are written in normalized dimensionless form by rescaling the time variable. Furthermore, an analogous circuit is designed by using the proposed method and built for verifying the new hyperchaos and the design method. Experimental results show a good agreement between numerical simulations and experimental results.
基金Supported by the National Natural Science Foundation of China (No. 60273093)the Natural Science Foundation of Zhejinag Province(No. Y104135) the Student Sci-entific Research Foundation of Ningbo university (No.C38).
文摘First the research is conducted on the design of the two-phase sinusoidal power clock gen- erator in this paper. Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks—Clocked Transmission Gate Adiabatic Logic (CTGAL) circuit is presented. This circuit makes use of the clocked transmission gates to sample the input signals, then the output loads are charged and discharged in a fully adiabatic manner by using bootstrapped N-Channel Metal Oxide Semiconductor (NMOS) and Complementary Metal Oxide Semiconductor (CMOS) latch structure. Finally, with the parameters of Taiwan Semiconductor Manufacturing Company (TSMC) 0.25μm CMOS device, the transient energy consumption of CTGAL, Bootstrap Charge-Recovery Logic (BCRL) and Pass-transistor Adiabatic Logic (PAL) including their clock generators is simulated. The simula-tion result indicates that CTGAL circuit has the characteristic of remarkably low energy consumption.
基金Supported by National Natural Science Foundation of Zhejiang Province
文摘The paper discusses general expressions of the clock signal and the next state equations containing the clock signal for flip-flops, and based on it, a unified theory for designing and analyzing both synchronous and asynchronous sequential circuits is proposed. The theory is proved effective by practical examples.
文摘Categories of earth-sheltered buildings were summarized, and it was proposed that landscape features of earth-sheltered buildings were demonstrated mainly as "ecological, landscape-like and systematic". Landscape elements such as entrance, road, water and greening were believed as major means of showing landscape features of earth-sheltered buildings. Entrance landscape design of such buildings was analyzed from the perspectives of plane-type, slope-type and step-type forms. Road design for these buildings should respect natural terrains so as to connect spaces and organize traffic routes reasonably. Waterscape design should take both landscape effects and loading capacity of roof into consideration so as to meet water-loving psychology of the public, virtual and real approaches should be combined to create waterscapes. Greening design of earth-sheltered buildings was explored from the perspectives of roof greening and vertical greening to improve the green coverage rate and show favorable ecological effects.
文摘This paper describes the design and implementation of a hydraulic circuit design system using case-based reasoning (CBR) paradigm from AI community The domain of hydraulic circuit design and case-based reasoning are briefly reviewed Then a proposed methodology in compuer-aided circuit design and dynamic leaning with the use of CBR is described Finally an application example is selected to illustrate the ussfulness of applying CBR in hydraulic circuit design with leaming.
基金the National Key Research and Development Program of China under Grant No.2018YFB2200403the National Natural Science Foundation of China under Grant Nos.11734001,91950204,92150302.
文摘The basic indexes of all-optical integrated photonic circuits include high-density integration,ultrafast response and ultralow energy consumption.Traditional methods mainly adopt conventional micro/nano-structures.The overall size of the circuit is large,usually reaches hundreds of microns.Besides,it is difficult to balance the ultrafast response and ultra-low energy consumption problem,and the crosstalk between two traditional devices is difficult to overcome.Here,we propose and experimentally demonstrate an approach based on inverse design method to realize a high-density,ultrafast and ultra-low energy consumption integrated photonic circuit with two all-optical switches controlling the input states of an all-optical XOR logic gate.The feature size of the whole circuit is only 2.5μm×7μm,and that of a single device is 2μm×2μm.The distance between two adjacent devices is as small as 1.5μm,within wavelength magnitude scale.Theoretical response time of the circuit is 150 fs,and the threshold energy is within 10 fJ/bit.We have also considered the crosstalk problem.The circuit also realizes a function of identifying two-digit logic signal results.Our work provides a new idea for the design of ultrafast,ultra-low energy consumption all-optical devices and the implementation of high-density photonic integrated circuits.
文摘In view of the limitations of a Rn-Gn model in the low frequency range and the defects of an En-In model in common use now, this paper builds a complete En-In model according to the theory of random harmonic. The parameters for the low-noise design such as the equivalent input noisy voltage Ens, the optimum source impedance Zsopt and the minimum noise figure Fmin can be calculated accurately by using this En-In model because it considers the coherence between the noise sources fully. Moreover, this paper points out that it will cause the maximum 30% miscalculation when neglecting the effects of the correlation coefficient 7. Using the series-series circuits as an example, this paper discusses the methods for the En-In noise analysis of electronic circuits preliminarily and demonstrates its correctness through the comparison between the simulated and measured results of the minimum noise figure Fmin of a single current series negative feedback circuit.
基金Project supported in part by the National Natural Science Foundation of China (Grant No. 61871429)the Natural Science Foundation of Zhejiang Province,China (Grant No. LY18F010012)the Project of Ministry of Science and Technology of China (Grant No. D20011)。
文摘A multi-valued logic system is a promising alternative to traditional binary logic because it can reduce the complexity,power consumption, and area of circuit implementation. This article briefly summarizes the development of ternary logic and its advantages in digital logic circuits. The schemes, characteristics, and application of ternary logic circuits based on CMOS, CNTFET, memristor, and other devices and processes are reviewed in this paper, providing some reference for the further research and development of ternary logic circuits.
基金the National Natural Science Fundation of China (60372001 90407007)the Ph. D. Programs Foundation of Ministry of Education of China (20030614006).
文摘Choosing the right characteristic parameter is the key to fault diagnosis in analog circuit. The featureevaluation and extraction methods based on neural network are presented. Parameter evaluation of circuit features is realized by training results from neural network; the superior nonlinear mapping capability is competent for extracting fault features which are normalized and compressed subsequently. The complex classification problem on fault pattern recognition in analog circuit is transferred into feature processing stage by feature extraction based on neural network effectively, which improves the diagnosis efficiency. A fault diagnosis illustration validated this method.
基金supported by the National Natural Science Foundation of China (No. 61474081)Guangxi Key Laboratory of Precision Navigation Technology and Application, Guilin University of Electronic Technology (No. DH201513)
文摘A double photodiode(PD) constructed by p^+/N-well junction and N-well/p-sub junction was designed and fabricated in a UMC 0.18-lm CMOS process. Based on the device structure and mechanism of double PD, a novel small-signal equivalent circuit model considering the carrier transit effect and the parasitic RC time constant was presented. By this model with complete electronic components, the double PD can be incorporated in a commercial circuit simulator. The component values were extracted by fitting the measured S-parameters using simulated annealing algorithm, and a good agreement between the measurement and the simulation results was achieved.
基金Supported by the NSF of China (# 69773034) and DARPA under contract # F33615-95-C-1627
文摘Based on analyzing significance of controlling clock in design of low power sequential circuits, this paper proposes a technique that the gating signal is derived from the master latch in a flip-flop to make the derived clock having no glitch and no skew. The design of a decimal counter with half-frequency division shows that by using the synchronous derived clock the counter has lower power dissipation as well as simpler combinational logic. Computer simulation shows 20% power saving.
基金supported in part by the NSF under Grant No.1704758,and the DARPA IDEA program.
文摘Realizing the layouts of analog/mixed-signal(AMS)integrated circuits(ICs)is a complicated task due to the high design flexibility and sensitive circuit performance.Compared with the advancements of digital IC layout automation,analog IC layout design is still heavily manual,which leads to a more time-consuming and error-prone process.In recent years,significant progress has been made in automated analog layout design with emerging of several open-source frameworks.This paper firstly reviews the existing state-of-the art AMS layout synthesis frameworks with focus on the different approaches and their individual challenges.We then present recent research trends and opportunities in the field.Finally,we summaries the paper with open questions and future directions for fully-automating the analog IC layout.
基金supported by the National Natural Science Foundation of China(Grant No.61174094)the Young Scientists Fund of the National Natural Science Foundation of China(Grant No.11202148)
文摘In this paper, the synchronization of the fractional-order generalized augmented Lu¨ system is investigated. Based on the predictor–corrector method, we obtain phase portraits, bifurcation diagrams, Lyapunov exponent spectra, and Poincare′maps of the fractional-order system and find that a four-wing chaotic attractor exists in the system when the system parameters change within certain ranges. Further, by varying the system parameters, rich dynamical behaviors occur in the2.7-order system. According to the stability theory of a fractional-order linear system, and adopting the linearization by feedback method, we have designed a nonlinear feedback controller in our theoretical analysis to implement the synchronization of the drive system with the response system. In addition, the synchronization is also shown by an electronic circuit implementation for the 2.7-order system. The obtained experiment results accord with the theoretical analyses,which further demonstrate the feasibility and effectiveness of the proposed synchronization scheme.
