The in-phase and quadrature-phase imbalance (IQI) is one of the major radio frequency impairments existing in orthogonal frequency division multiplexing (OFDM) systems with direct-conversion transceivers. During the t...The in-phase and quadrature-phase imbalance (IQI) is one of the major radio frequency impairments existing in orthogonal frequency division multiplexing (OFDM) systems with direct-conversion transceivers. During the transmission of the communication signal, the impact of IQI is coupled with channel impulse responses (CIR), which makes the traditional channel estimation schemes ineffective. A decoupled estimation scheme is proposed to separately estimate the frequency-dependent IQI and wireless channel. Firstly, the generalized channel model is built to separate the parameters of IQI and wireless channel. Then an iterative estimation scheme of frequency-dependent IQI is designed at the initial stage of communication. Finally, based on the estimation result of IQI, the least square algorithm is utilized to estimate the channel-related parameters at each time of channel variation. Compared with the joint estimation schemes of IQI and channel, the proposed decoupled estimation scheme requires much lower training overhead at each time of channel variation. Simulation results demonstrate the good estimation performance of the proposed scheme.展开更多
A dual-band direct-conversion WLAN transceiver baseband compliant with the IEEE 802.11 a/b/g standards is described. Several critical techniques for receiver DC offset compensation and transmitter carrier leakage reje...A dual-band direct-conversion WLAN transceiver baseband compliant with the IEEE 802.11 a/b/g standards is described. Several critical techniques for receiver DC offset compensation and transmitter carrier leakage rejection calibration are presented that enable the direct-conversion architecture to meet all WLAN specifications. The receiver baseband VGA provides 62 dB gain range with steps of 2 dB and a DC offset cancellation circuit is introduced to remove the offset from layout and self-mixing. The calibration loop achieves constant high-pass pole when gain changes; and a fast response time by programming the pole to 1 MHz during preamble and to 30 kHz during receiving data. The transmitter baseband employs an auto-calibration loop with on-chip AD and DA to suppress the carrier leakage, and AD can be powered down after calibration to save power consumption. The chip consumes 17.52 mA for RX baseband VGA and DCOC, and 8.3 mA for TX carrier leakage calibration （5.88 mA after calibration） from 2.85 V supply. Implemented in a 0.35μm SiGe technology, they occupy 0.68 mm^2 and 0.18 mma die size respectively.展开更多
A dual-band reconfigurable wireless receiver RF front-end is presented, which is based on the directconversion principle and consists of a low noise amplifer （LNA） and a down-converter. By utilizing a compact switch...A dual-band reconfigurable wireless receiver RF front-end is presented, which is based on the directconversion principle and consists of a low noise amplifer （LNA） and a down-converter. By utilizing a compact switchable on-chip symmetrical inductor, the RF front-end could be switched between two operation frequency bands without extra die area cost. This RF front-end has been implemented in the 180 nm CMOS process and the measured results show that the front-end could provide a gain of 25 dB and IIP3 of 6 dBm at 2.2 GHz, and a gain of 18.8 dB and IIP3 of 7.3 dBm at 4.5 GHz. The whole front-end consumes 12 mA current at 1.2 V voltage supply for the LNA and 2.1 mA current at 1.8 V for the mixer, with a die area of 1.2 × 1 mm^2.展开更多
A fully integrated direct-conversion digital satellite tuner for DVB-S/S2 and ABS-S applications is presented.A broadband noise-canceling Balun-LNA and passive quadrature mixers provided a high-linearity low noise RF ...A fully integrated direct-conversion digital satellite tuner for DVB-S/S2 and ABS-S applications is presented.A broadband noise-canceling Balun-LNA and passive quadrature mixers provided a high-linearity low noise RF front-end,while the synthesizer integrated the loop filter to reduce the solution cost and system debug time.Fabricated in 0.18μm CMOS,the chip achieves a less than 7.6 dB noise figure over a 900-2150 MHz L-band, while the measured sensitivity for 4.42 MS/s QPSK-3/4 mode is -91 dBm at the PCB connector.The fully integrated integer-N synthesizer operating from 2150 to 4350 MHz achieves less than 1℃integrated phase error. The chip consumes about 145 mA at a 3.3 V supply with internal integrated LDOs.展开更多
A fully integrated low power transmitter for an IEEE 802. llb transceiver system is implemented in SMIC 0.18μm technology. The direct-conversion transmitter includes two Chebyshev I low pass filters,two PGAs,a SSB mi...A fully integrated low power transmitter for an IEEE 802. llb transceiver system is implemented in SMIC 0.18μm technology. The direct-conversion transmitter includes two Chebyshev I low pass filters,two PGAs,a SSB mixer, and a PA driver. The transmitter provides a gain control of 32dB in 3dB steps. The maximum output power is - 3.4dBm and the EVM is 6. 8%. The power consumption of the transmitter is only 57.6mW with a 1.8V power supply. The chip area of the transmitter is 1.6mm × 1.6mm.展开更多
In recent years, much attention has been paid to software-defined radio （SDR） technologies for multimode wireless systems SDR can be defined as a radio communication system that uses software to modulate and demodul...In recent years, much attention has been paid to software-defined radio （SDR） technologies for multimode wireless systems SDR can be defined as a radio communication system that uses software to modulate and demodulate radio signals. This article describes concepts, theory, and design principles for SDR down-conversion and up-conversion. Design issues in SDR down-conversion are discussed, and two different architectures, super-heterodyne and direct-conversion, are proposed. Design issues in SDR up-conversion are also discussed, and trade-offs in the design of filters, mixers, NCO, DAC, and signal processing are highlighted.展开更多
A 2.4 GHz low-power,low-noise and highly linear receiver front-end with a low noise amplifier（LNA） and balun optimization is presented.Direct conversion architecture is employed for this front-end.The on-chip balun ...A 2.4 GHz low-power,low-noise and highly linear receiver front-end with a low noise amplifier（LNA） and balun optimization is presented.Direct conversion architecture is employed for this front-end.The on-chip balun is designed for single-to-differential conversion between the LNA and the down-conversion mixer,and is optimized for the best noise performance of the front-end.The circuit is implemented with 0.35μm SiGe BiCMOS technology.The front-end has three gain steps for maximization of the input dynamic range.The overall maximum gain is about 36 dB.The double-sideband noise figure is 3.8 dB in high gain mode and the input referred third-order intercept point is 12.5 dBm in low gain mode.The down-conversion mixer has a tunable parallel R-C load at the output and an emitter follower is used as the output stage for testing purposes.The total front-end dissipation is 33 mW under a 2.85 V supply and occupies a 0.66 mm^2 die size.展开更多
A single-chip low-power transceiver IC operating in the 2.4 GHz ISM band is presented. Designed in 0.18μm CMOS, the transceiver system employs direct-conversion architecture for both the receiver and transmitter to r...A single-chip low-power transceiver IC operating in the 2.4 GHz ISM band is presented. Designed in 0.18μm CMOS, the transceiver system employs direct-conversion architecture for both the receiver and transmitter to realize a fully integrated wireless LAN product. A sigma-delta （∑△） fractional-N frequency synthesizer provides on-chip quadrature local oscillator frequency. Measurement results show that the receiver achieves a maximum gain of 81 dB and a noise figure of 8.2 dB, the transmitter has maximum output power of -3.4 dBm and RMS EVM of 6.8%. Power dissipation of the transceiver is 74 mW in the receiving mode and 81 mW in the transmitting mode under a supply voltage of 1.8 V, including 30 mW consumed by the frequency synthesizer. The total chip area with pads is 2.7 × 4.2 mm^2.展开更多
A carrier leakage calibration and compensation technique based on digital baseband for a wideband wireless communication transceiver is proposed. The digital baseband transmits a calibration signal, samples the signal...A carrier leakage calibration and compensation technique based on digital baseband for a wideband wireless communication transceiver is proposed. The digital baseband transmits a calibration signal, samples the signal which passes through the transmitter path and the calibration loop in the RF chip, measures the carrier leakage by analyzing the sampled data and compensates it. Compared with a self-calibration technique in the RF chip, the proposed technique saves area and power consumption for the wireless local area network （WLAN） solution. This technique has been successfully used for 802.1 In system and satisfies the requirement of the standard by achieving over 50 dB carrier leakage suppression.展开更多
A novel low power RF receiver front-end for 3-5 GHz UWB is presented. Designed in the 0.13μm CMOS process, the direct conversion receiver features a wideband balun-coupled noise cancelling transconductance input stag...A novel low power RF receiver front-end for 3-5 GHz UWB is presented. Designed in the 0.13μm CMOS process, the direct conversion receiver features a wideband balun-coupled noise cancelling transconductance input stage, followed by quadrature passive mixers and transimpedance loading amplifiers. Measurement results show that the receiver achieves an input return loss below -8.5 dB across the 3.1-4.7 GHz frequency range, maximum voltage conversion gain of 27 dB, minimum noise figure of 4 dB, IIP3 of -11.5 dBm, and IIP2 of 33 dBm. Working under 1.2 V supply voltage, the receiver consumes total current of 18 mA including 10 mA by on-chip quadrature LO signal generation and buffer circuits. The chip area with pads is 1.1 × 1.5 mm^2.展开更多
基金supported by the National Natural Science Foundation of China(6140123261471200+4 种基金6150124861501254)the China Postdoctoral Science Foundation(2014M561692)the Jiangsu Province Postdoctoral Science Foundation(1402087C)the NUPTSF(NY213063)
文摘The in-phase and quadrature-phase imbalance (IQI) is one of the major radio frequency impairments existing in orthogonal frequency division multiplexing (OFDM) systems with direct-conversion transceivers. During the transmission of the communication signal, the impact of IQI is coupled with channel impulse responses (CIR), which makes the traditional channel estimation schemes ineffective. A decoupled estimation scheme is proposed to separately estimate the frequency-dependent IQI and wireless channel. Firstly, the generalized channel model is built to separate the parameters of IQI and wireless channel. Then an iterative estimation scheme of frequency-dependent IQI is designed at the initial stage of communication. Finally, based on the estimation result of IQI, the least square algorithm is utilized to estimate the channel-related parameters at each time of channel variation. Compared with the joint estimation schemes of IQI and channel, the proposed decoupled estimation scheme requires much lower training overhead at each time of channel variation. Simulation results demonstrate the good estimation performance of the proposed scheme.
文摘A dual-band direct-conversion WLAN transceiver baseband compliant with the IEEE 802.11 a/b/g standards is described. Several critical techniques for receiver DC offset compensation and transmitter carrier leakage rejection calibration are presented that enable the direct-conversion architecture to meet all WLAN specifications. The receiver baseband VGA provides 62 dB gain range with steps of 2 dB and a DC offset cancellation circuit is introduced to remove the offset from layout and self-mixing. The calibration loop achieves constant high-pass pole when gain changes; and a fast response time by programming the pole to 1 MHz during preamble and to 30 kHz during receiving data. The transmitter baseband employs an auto-calibration loop with on-chip AD and DA to suppress the carrier leakage, and AD can be powered down after calibration to save power consumption. The chip consumes 17.52 mA for RX baseband VGA and DCOC, and 8.3 mA for TX carrier leakage calibration （5.88 mA after calibration） from 2.85 V supply. Implemented in a 0.35μm SiGe technology, they occupy 0.68 mm^2 and 0.18 mma die size respectively.
基金Project supported by the National Natural Science Foundation of China (No.60806008)the Fok Ying Tung Education Foundation (No.104028)
文摘A dual-band reconfigurable wireless receiver RF front-end is presented, which is based on the directconversion principle and consists of a low noise amplifer （LNA） and a down-converter. By utilizing a compact switchable on-chip symmetrical inductor, the RF front-end could be switched between two operation frequency bands without extra die area cost. This RF front-end has been implemented in the 180 nm CMOS process and the measured results show that the front-end could provide a gain of 25 dB and IIP3 of 6 dBm at 2.2 GHz, and a gain of 18.8 dB and IIP3 of 7.3 dBm at 4.5 GHz. The whole front-end consumes 12 mA current at 1.2 V voltage supply for the LNA and 2.1 mA current at 1.8 V for the mixer, with a die area of 1.2 × 1 mm^2.
基金Project supported by the National High Technology Research and Development Program of China(No2007AA01Z280)
文摘A fully integrated direct-conversion digital satellite tuner for DVB-S/S2 and ABS-S applications is presented.A broadband noise-canceling Balun-LNA and passive quadrature mixers provided a high-linearity low noise RF front-end,while the synthesizer integrated the loop filter to reduce the solution cost and system debug time.Fabricated in 0.18μm CMOS,the chip achieves a less than 7.6 dB noise figure over a 900-2150 MHz L-band, while the measured sensitivity for 4.42 MS/s QPSK-3/4 mode is -91 dBm at the PCB connector.The fully integrated integer-N synthesizer operating from 2150 to 4350 MHz achieves less than 1℃integrated phase error. The chip consumes about 145 mA at a 3.3 V supply with internal integrated LDOs.
文摘A fully integrated low power transmitter for an IEEE 802. llb transceiver system is implemented in SMIC 0.18μm technology. The direct-conversion transmitter includes two Chebyshev I low pass filters,two PGAs,a SSB mixer, and a PA driver. The transmitter provides a gain control of 32dB in 3dB steps. The maximum output power is - 3.4dBm and the EVM is 6. 8%. The power consumption of the transmitter is only 57.6mW with a 1.8V power supply. The chip area of the transmitter is 1.6mm × 1.6mm.
文摘In recent years, much attention has been paid to software-defined radio （SDR） technologies for multimode wireless systems SDR can be defined as a radio communication system that uses software to modulate and demodulate radio signals. This article describes concepts, theory, and design principles for SDR down-conversion and up-conversion. Design issues in SDR down-conversion are discussed, and two different architectures, super-heterodyne and direct-conversion, are proposed. Design issues in SDR up-conversion are also discussed, and trade-offs in the design of filters, mixers, NCO, DAC, and signal processing are highlighted.
文摘A 2.4 GHz low-power,low-noise and highly linear receiver front-end with a low noise amplifier（LNA） and balun optimization is presented.Direct conversion architecture is employed for this front-end.The on-chip balun is designed for single-to-differential conversion between the LNA and the down-conversion mixer,and is optimized for the best noise performance of the front-end.The circuit is implemented with 0.35μm SiGe BiCMOS technology.The front-end has three gain steps for maximization of the input dynamic range.The overall maximum gain is about 36 dB.The double-sideband noise figure is 3.8 dB in high gain mode and the input referred third-order intercept point is 12.5 dBm in low gain mode.The down-conversion mixer has a tunable parallel R-C load at the output and an emitter follower is used as the output stage for testing purposes.The total front-end dissipation is 33 mW under a 2.85 V supply and occupies a 0.66 mm^2 die size.
基金supported by the National Natural Science Foundation of China (No. 60606009)
文摘A single-chip low-power transceiver IC operating in the 2.4 GHz ISM band is presented. Designed in 0.18μm CMOS, the transceiver system employs direct-conversion architecture for both the receiver and transmitter to realize a fully integrated wireless LAN product. A sigma-delta （∑△） fractional-N frequency synthesizer provides on-chip quadrature local oscillator frequency. Measurement results show that the receiver achieves a maximum gain of 81 dB and a noise figure of 8.2 dB, the transmitter has maximum output power of -3.4 dBm and RMS EVM of 6.8%. Power dissipation of the transceiver is 74 mW in the receiving mode and 81 mW in the transmitting mode under a supply voltage of 1.8 V, including 30 mW consumed by the frequency synthesizer. The total chip area with pads is 2.7 × 4.2 mm^2.
文摘A carrier leakage calibration and compensation technique based on digital baseband for a wideband wireless communication transceiver is proposed. The digital baseband transmits a calibration signal, samples the signal which passes through the transmitter path and the calibration loop in the RF chip, measures the carrier leakage by analyzing the sampled data and compensates it. Compared with a self-calibration technique in the RF chip, the proposed technique saves area and power consumption for the wireless local area network （WLAN） solution. This technique has been successfully used for 802.1 In system and satisfies the requirement of the standard by achieving over 50 dB carrier leakage suppression.
基金supported by the National Natural Science Foundation of China (No. 60606009).
文摘A novel low power RF receiver front-end for 3-5 GHz UWB is presented. Designed in the 0.13μm CMOS process, the direct conversion receiver features a wideband balun-coupled noise cancelling transconductance input stage, followed by quadrature passive mixers and transimpedance loading amplifiers. Measurement results show that the receiver achieves an input return loss below -8.5 dB across the 3.1-4.7 GHz frequency range, maximum voltage conversion gain of 27 dB, minimum noise figure of 4 dB, IIP3 of -11.5 dBm, and IIP2 of 33 dBm. Working under 1.2 V supply voltage, the receiver consumes total current of 18 mA including 10 mA by on-chip quadrature LO signal generation and buffer circuits. The chip area with pads is 1.1 × 1.5 mm^2.
