In this paper, the impact of limiting thermostat on the rupture event occuring in Fuel-Oil burner fuel pre-heaters＇ resistant （heat generating） wires is inspected numerically. Gaseous fuel content in the pipeline h...In this paper, the impact of limiting thermostat on the rupture event occuring in Fuel-Oil burner fuel pre-heaters＇ resistant （heat generating） wires is inspected numerically. Gaseous fuel content in the pipeline has also been issued as a possibility. Heater＇s inner temperature distributions have been simulated by an in-house MATrix LABoratory （MATLAB） script in order to understand the resistant wire exposure to high temperatures by numerous scenarios. It is concluded that the effect of fuel flowrate is not a major effect on the wires＇ fate because of the limiting thermostat co-working. The main difference between the calculations is the effect of thermostat cut off function. The numerical simulations enlightened the dominant effect of thermostat sensing delay, so the overheating event. Intolerable delay results with a quick drop in the thermal efficiency and an increased possibility on wire rupture due to overheating which means a burner malfunction. Referring to the first numerical simulation results, a distributed and reduced heat flux was implemented with the same fluid and thermodynamic properties on a revised pre-heater model with an increased heater plate. The increment, thus the reduction on the heat flux of the ribbon wires has been noted as the key for safe operation.展开更多
Considering the self-heating effect, an accurate expression for the global interconnection resistance per unit length in terms of interconnection wire width and spacing is presented. Based on the proposed resistance m...Considering the self-heating effect, an accurate expression for the global interconnection resistance per unit length in terms of interconnection wire width and spacing is presented. Based on the proposed resistance model and according to the trade-off theory, a novel optimization analytical model of delay, power dissipation and bandwidth is derived. The proposed optimal model is verified and compared based on 90 nm, 65 nm and 40 nm CMOS technologies. It can be found that more optimum results can be easily obtained by the proposed model. This optimization model is more accurate and realistic than the conventional optimization models, and can be integrated into the global interconnection design ofnano-scale integrated circuits.展开更多
文摘In this paper, the impact of limiting thermostat on the rupture event occuring in Fuel-Oil burner fuel pre-heaters＇ resistant （heat generating） wires is inspected numerically. Gaseous fuel content in the pipeline has also been issued as a possibility. Heater＇s inner temperature distributions have been simulated by an in-house MATrix LABoratory （MATLAB） script in order to understand the resistant wire exposure to high temperatures by numerous scenarios. It is concluded that the effect of fuel flowrate is not a major effect on the wires＇ fate because of the limiting thermostat co-working. The main difference between the calculations is the effect of thermostat cut off function. The numerical simulations enlightened the dominant effect of thermostat sensing delay, so the overheating event. Intolerable delay results with a quick drop in the thermal efficiency and an increased possibility on wire rupture due to overheating which means a burner malfunction. Referring to the first numerical simulation results, a distributed and reduced heat flux was implemented with the same fluid and thermodynamic properties on a revised pre-heater model with an increased heater plate. The increment, thus the reduction on the heat flux of the ribbon wires has been noted as the key for safe operation.
基金supported by the National Natural Science Foundation of China(No.60606006)the Key Science&Technology Special Project of Shaanxi Province,China(No.2011KTCQ01-19)the National Defense Pre-Research Foundation of China(No.9140A23060111)
文摘Considering the self-heating effect, an accurate expression for the global interconnection resistance per unit length in terms of interconnection wire width and spacing is presented. Based on the proposed resistance model and according to the trade-off theory, a novel optimization analytical model of delay, power dissipation and bandwidth is derived. The proposed optimal model is verified and compared based on 90 nm, 65 nm and 40 nm CMOS technologies. It can be found that more optimum results can be easily obtained by the proposed model. This optimization model is more accurate and realistic than the conventional optimization models, and can be integrated into the global interconnection design ofnano-scale integrated circuits.
