With research on the carrier phase synchronization and symbol synchronization algorithm of demodulation module, a synchronization circuit system is designed for GPS software receiver based on field programmable gate a...With research on the carrier phase synchronization and symbol synchronization algorithm of demodulation module, a synchronization circuit system is designed for GPS software receiver based on field programmable gate array （FPGA）, and a series of experiment is done on the hardware platform. The result shows the all-digital synchronization and demodulation of GPS intermediate frequency （IF） signal can be realized and applied in embedded real-time GPS software receiver system. It is verified that the decision-directed joint tracking algorithm of carrier phase and symbol timing for received signals from GPS is reasonable. In addition, the loop works steadily and can be used for receiving GPS signals using synchronous demodulation. The synchronization circuit for GPS software receiver designed based on FPGA has the features of low cost, miniaturization, low power and real-time. Surely, it will become one of the development directions for GPS and even GNSS embedded real-time software receiver.展开更多
We demonstrate a piezoelectric vibration energy harvester with the ZnO piezoelectric film and an improved synchronous electric charge extraction energy harvesting circuit on the basis of the beam-type mechanical struc...We demonstrate a piezoelectric vibration energy harvester with the ZnO piezoelectric film and an improved synchronous electric charge extraction energy harvesting circuit on the basis of the beam-type mechanical structure,especially investigate its output performance in vibration harvesting and ability to generate charges.By establishing the theoretical model for each of vibration and circuit,the numerical results of voltage and power output are obtained.By fabricating the prototype of this harvester,the quality of the sputtered film is explored.Theoretical and experimental analyses are conducted in open-circuit and closed-circuit conditions,where the open-circuit mode refers to the voltage output in relation to the ZnO film and external excitation,and the power output of the closed-circuit mode is relevant to resistance.Experimental findings show good agreement with the theoretical ones,in the output tendency.It is observed that the properties of ZnO film achieve regularly direct proportion to output performance under different excitations.Furthermore,a maximum experimental power output of 4.5 mW in a resistance range of 3 kΩ-8 kΩis achieved by using an improved synchronous electric charge extraction circuit.The result is not only more than three times the power output of classic circuit,but also can broaden the resistance to a large range of 5 kΩunder an identical maximum value of power output.In this study we demonstrate the fundamental mechanism of piezoelectric materials under multiple conditions and take an example to show the methods of fabricating and testing the ZnO film.Furthermore,it may contribute to a novel energy harvesting circuit with high output performance.展开更多
An explicit analytical solution is presented for unidirectionally coupled two Murali-Lakshmanan-Chua circuits exhibiting chaos synchronization in their dynamics. The transition of the system from an unsynchronized sta...An explicit analytical solution is presented for unidirectionally coupled two Murali-Lakshmanan-Chua circuits exhibiting chaos synchronization in their dynamics. The transition of the system from an unsynchronized state to a state of complete synchronization under the influence of the coupling parameter is observed through phase portraits obtained from the analytical solutions of the circuit equations characterizing the system.展开更多
The paper proposes an ATPG method for the Synchronous Sequential circuits described in synthesizable VHDL behavioral RTL. The method extracts a controlling tree for each process in the behavioral description and forms...The paper proposes an ATPG method for the Synchronous Sequential circuits described in synthesizable VHDL behavioral RTL. The method extracts a controlling tree for each process in the behavioral description and forms a graph to represent the static data-flow for the target circuit. A fault-model is defined at RT-Level. The ATPG method is then presented. Experimental results show that the ATPG method is time effective and can generate tests with fairly good quality, the fault coverage of some circuits is to be enhanced though.展开更多
The paper proposes a low power non-volatile baseband processor with wake-up identification(WUI) receiver for LR-WPAN transceiver.It consists of WUI receiver,main receiver,transmitter,non-volatile memory(NVM) and power...The paper proposes a low power non-volatile baseband processor with wake-up identification(WUI) receiver for LR-WPAN transceiver.It consists of WUI receiver,main receiver,transmitter,non-volatile memory(NVM) and power management module.The main receiver adopts a unified simplified synchronization method and channel codec with proactive Reed-Solomon Bypass technique,which increases the robustness and energy efficiency of receiver.The WUI receiver specifies the communication node and wakes up the transceiver to reduce average power consumption of the transceiver.The embedded NVM can backup/restore the states information of processor that avoids the loss of the state information caused by power failure and reduces the unnecessary power of repetitive computation when the processor is waked up from power down mode.The baseband processor is designed and verified on a FPGA board.The simulated power consumption of processor is 5.1uW for transmitting and 28.2μW for receiving.The WUI receiver technique reduces the average power consumption of transceiver remarkably.If the transceiver operates 30 seconds in every 15 minutes,the average power consumption of the transceiver can be reduced by two orders of magnitude.The NVM avoids the loss of the state information caused by power failure and energy waste caused by repetitive computation.展开更多
In this paper, a novel structure of a high-precision synchronization circuit, HPSC, using interleaved delay units and a dynamic compensation circuit is proposed. HPSCs are designed for synchronization of clock distrib...In this paper, a novel structure of a high-precision synchronization circuit, HPSC, using interleaved delay units and a dynamic compensation circuit is proposed. HPSCs are designed for synchronization of clock distribution networks in large-scale integrated circuits, where high-quality clocks are required. The application of a hybrid structure of a coarse delay line and dynamic compensation circuit performs roughly the alignment of the clock signal in two clock cycles, and finishes the fine tuning in the next three clock cycles with the phase error suppressed under 3.8 ps. The proposed circuit is implemented and fabricated using a SMIC 0.13 μm 1P6M process with a supply voltage at 1.2 V. The allowed operation frequency ranges from 200 to 800 MHz, and the duty cycle ranges between [20%, 80%]. The active area of the core circuits is 245 × 134 μm2, and the power consumption is 1.64 mW at 500 MHz.展开更多
基金supported in part by the National High Technology Research and Development Program of China (863 Program)(2006AA12A108)CSC International Scholarship (2008104769)
文摘With research on the carrier phase synchronization and symbol synchronization algorithm of demodulation module, a synchronization circuit system is designed for GPS software receiver based on field programmable gate array （FPGA）, and a series of experiment is done on the hardware platform. The result shows the all-digital synchronization and demodulation of GPS intermediate frequency （IF） signal can be realized and applied in embedded real-time GPS software receiver system. It is verified that the decision-directed joint tracking algorithm of carrier phase and symbol timing for received signals from GPS is reasonable. In addition, the loop works steadily and can be used for receiving GPS signals using synchronous demodulation. The synchronization circuit for GPS software receiver designed based on FPGA has the features of low cost, miniaturization, low power and real-time. Surely, it will become one of the development directions for GPS and even GNSS embedded real-time software receiver.
文摘We demonstrate a piezoelectric vibration energy harvester with the ZnO piezoelectric film and an improved synchronous electric charge extraction energy harvesting circuit on the basis of the beam-type mechanical structure,especially investigate its output performance in vibration harvesting and ability to generate charges.By establishing the theoretical model for each of vibration and circuit,the numerical results of voltage and power output are obtained.By fabricating the prototype of this harvester,the quality of the sputtered film is explored.Theoretical and experimental analyses are conducted in open-circuit and closed-circuit conditions,where the open-circuit mode refers to the voltage output in relation to the ZnO film and external excitation,and the power output of the closed-circuit mode is relevant to resistance.Experimental findings show good agreement with the theoretical ones,in the output tendency.It is observed that the properties of ZnO film achieve regularly direct proportion to output performance under different excitations.Furthermore,a maximum experimental power output of 4.5 mW in a resistance range of 3 kΩ-8 kΩis achieved by using an improved synchronous electric charge extraction circuit.The result is not only more than three times the power output of classic circuit,but also can broaden the resistance to a large range of 5 kΩunder an identical maximum value of power output.In this study we demonstrate the fundamental mechanism of piezoelectric materials under multiple conditions and take an example to show the methods of fabricating and testing the ZnO film.Furthermore,it may contribute to a novel energy harvesting circuit with high output performance.
文摘An explicit analytical solution is presented for unidirectionally coupled two Murali-Lakshmanan-Chua circuits exhibiting chaos synchronization in their dynamics. The transition of the system from an unsynchronized state to a state of complete synchronization under the influence of the coupling parameter is observed through phase portraits obtained from the analytical solutions of the circuit equations characterizing the system.
基金supported by National Natural Science Foundation of China under grant No.69733010.
文摘The paper proposes an ATPG method for the Synchronous Sequential circuits described in synthesizable VHDL behavioral RTL. The method extracts a controlling tree for each process in the behavioral description and forms a graph to represent the static data-flow for the target circuit. A fault-model is defined at RT-Level. The ATPG method is then presented. Experimental results show that the ATPG method is time effective and can generate tests with fairly good quality, the fault coverage of some circuits is to be enhanced though.
基金supported in part by the National Natural Science Foundation of China(No.61306027)
文摘The paper proposes a low power non-volatile baseband processor with wake-up identification(WUI) receiver for LR-WPAN transceiver.It consists of WUI receiver,main receiver,transmitter,non-volatile memory(NVM) and power management module.The main receiver adopts a unified simplified synchronization method and channel codec with proactive Reed-Solomon Bypass technique,which increases the robustness and energy efficiency of receiver.The WUI receiver specifies the communication node and wakes up the transceiver to reduce average power consumption of the transceiver.The embedded NVM can backup/restore the states information of processor that avoids the loss of the state information caused by power failure and reduces the unnecessary power of repetitive computation when the processor is waked up from power down mode.The baseband processor is designed and verified on a FPGA board.The simulated power consumption of processor is 5.1uW for transmitting and 28.2μW for receiving.The WUI receiver technique reduces the average power consumption of transceiver remarkably.If the transceiver operates 30 seconds in every 15 minutes,the average power consumption of the transceiver can be reduced by two orders of magnitude.The NVM avoids the loss of the state information caused by power failure and energy waste caused by repetitive computation.
文摘In this paper, a novel structure of a high-precision synchronization circuit, HPSC, using interleaved delay units and a dynamic compensation circuit is proposed. HPSCs are designed for synchronization of clock distribution networks in large-scale integrated circuits, where high-quality clocks are required. The application of a hybrid structure of a coarse delay line and dynamic compensation circuit performs roughly the alignment of the clock signal in two clock cycles, and finishes the fine tuning in the next three clock cycles with the phase error suppressed under 3.8 ps. The proposed circuit is implemented and fabricated using a SMIC 0.13 μm 1P6M process with a supply voltage at 1.2 V. The allowed operation frequency ranges from 200 to 800 MHz, and the duty cycle ranges between [20%, 80%]. The active area of the core circuits is 245 × 134 μm2, and the power consumption is 1.64 mW at 500 MHz.
