High spectral efficiency is essential in design of multimedia communication systems such as L-band mobile in addition to various requirements of transmission quality. Time-interleaved A/D converter （TI-ADC） is an ef...High spectral efficiency is essential in design of multimedia communication systems such as L-band mobile in addition to various requirements of transmission quality. Time-interleaved A/D converter （TI-ADC） is an effective candidate to implement wide-band ADC with relatively slow circuits accounting for digital spectrum management. However, practical performance of TI-ADC is largely limited because of mismatches between different channels originated from manufacturing process variations. In this paper, a blind adaptive method is proposed to correct gain mismatch errors in TI-ADC, and it is verified through simulations on a two-channel TI-ADC. In proposed method, gain mismatch error is estimated and corrected in an adaptive scheme. Proposed compensated T1-ADC architecture is structurally very simple and hence suitable for realiza- tion in integrated circuits. Besides, proposed digital compensation algorithm not only is computationally efficient but also provides an improvement of 32.7 dB in the performance of two-channel TI ADC.展开更多
This paper proposes a digital background calibration scheme for timing skew in time-interleaved analog-to-digital converters (TIADCs). It detects the relevant timing error by subtracting the output difference with the...This paper proposes a digital background calibration scheme for timing skew in time-interleaved analog-to-digital converters (TIADCs). It detects the relevant timing error by subtracting the output difference with the sum of the first derivative of the digital output. The least-mean-square (LMS) loop is exploited to compensate the timing skew. Since the calibration scheme depends on the digital output, all timing skew sources can be calibrated and the main ADC is maintained. The proposed scheme is effective within the entire frequency range of 0 ? fs/2. Compared with traditional calibration schemes, the proposed approach is more feasible and consumes significantly lesser power and smaller area.展开更多
A sampling switch with an embedded digital-to-skew converter(DSC) is presented.The proposed switch eliminates time-interleaved ADCs' skews by adjusting the boosted voltage.A similar bridged capacitors' charge ...A sampling switch with an embedded digital-to-skew converter(DSC) is presented.The proposed switch eliminates time-interleaved ADCs' skews by adjusting the boosted voltage.A similar bridged capacitors' charge sharing structure is used to minimize the area.The circuit is fabricated in a 0.18μm CMOS process and achieves sub-1 ps resolution and 200 ps timing range at a rate of 100 MS/s.The power consumption is 430μW at maximum.The measurement result also includes a 2-channel 14-bit 100 MS/s time-interleaved ADCs(TI-ADCs) with the proposed DSC switch's demonstration.This scheme is widely applicable for the clock skew and aperture error calibration demanded in TI-ADCs and SHA-less ADCs.展开更多
为了解决传统双向DC/DC变换器的损耗较大和效率较低等实际问题,提出了一种将交错并联磁集成技术与软开关技术相结合的控制方法。首先,以三相交错并联磁集成双向DC/DC变换器为研究实例,分析了当变换器分别运行在一、二、三相电感时的3种...为了解决传统双向DC/DC变换器的损耗较大和效率较低等实际问题,提出了一种将交错并联磁集成技术与软开关技术相结合的控制方法。首先,以三相交错并联磁集成双向DC/DC变换器为研究实例,分析了当变换器分别运行在一、二、三相电感时的3种工作状态。在每种状态下,分别讨论了电感反向电流的持续时间和死区时间,从而总结出了变换器运行在每种状态下可以实现零电压开关(zero voltage switch,ZVS)的条件。最后,通过实验进一步验证了理论分析的正确性,证实了该设计方案的实用性。展开更多
提出了一种双通道可重构14 bit 125 MS/s流水线模数转换器(ADC).该双通道14 bit ADC可工作在并行双通道14 bit 125 MS/s、时间交织14 bit 250 MS/s以及求和15 bit 125 MS/s三种模式.为抑制通道间失配误差的影响,提出一种数模混合前台校...提出了一种双通道可重构14 bit 125 MS/s流水线模数转换器(ADC).该双通道14 bit ADC可工作在并行双通道14 bit 125 MS/s、时间交织14 bit 250 MS/s以及求和15 bit 125 MS/s三种模式.为抑制通道间失配误差的影响,提出一种数模混合前台校准技术.为减少ADC输出端口数目,数据输出由高速串行数据发送器驱动,并且其工作模式有1.75,2,3.5 Gbit/s三种.该ADC电路采用0.18μm 1P5M 1.8 V CMOS工艺实现,测试结果表明,对于相同的10.1 MHz的输入信号,该ADC电路在14 bit 125 MS/s模式下的SNR和SFDR分别为72.5 dBFS和83.1dB,在14 bit 250 MS/s模式下的SNR和SFDR分别为71.3 dBFS和77.6 dB,在15 bit 125 MS/s模式下的SNR和SFDR分别为75.3 dBFS和87.4 dB.芯片总体功耗为461 mW,单通道ADC内核功耗为210 mW,面积为1.3×4 mm^2.展开更多
提出了一种基于TMS320VC549定点DSP微处理器芯片的语音信号压缩/解压缩处理系统。该系统采用TLC320AD50C模数、数模转换器,采样率为8 kHz,处理能力为100 M IPS。系统配置有大容量存储器,具备资源扩展能力,适用于语音信号压缩/解压缩和...提出了一种基于TMS320VC549定点DSP微处理器芯片的语音信号压缩/解压缩处理系统。该系统采用TLC320AD50C模数、数模转换器,采样率为8 kHz,处理能力为100 M IPS。系统配置有大容量存储器,具备资源扩展能力,适用于语音信号压缩/解压缩和语音识别、语音合成等其他领域。实验结果表明,系统对语音信号的压缩解压缩处理具有稳定性、灵活性和通用性。展开更多
基金Iran’s Telecommunication Research Center(ITRC)(No.500/3653)
文摘High spectral efficiency is essential in design of multimedia communication systems such as L-band mobile in addition to various requirements of transmission quality. Time-interleaved A/D converter （TI-ADC） is an effective candidate to implement wide-band ADC with relatively slow circuits accounting for digital spectrum management. However, practical performance of TI-ADC is largely limited because of mismatches between different channels originated from manufacturing process variations. In this paper, a blind adaptive method is proposed to correct gain mismatch errors in TI-ADC, and it is verified through simulations on a two-channel TI-ADC. In proposed method, gain mismatch error is estimated and corrected in an adaptive scheme. Proposed compensated T1-ADC architecture is structurally very simple and hence suitable for realiza- tion in integrated circuits. Besides, proposed digital compensation algorithm not only is computationally efficient but also provides an improvement of 32.7 dB in the performance of two-channel TI ADC.
文摘This paper proposes a digital background calibration scheme for timing skew in time-interleaved analog-to-digital converters (TIADCs). It detects the relevant timing error by subtracting the output difference with the sum of the first derivative of the digital output. The least-mean-square (LMS) loop is exploited to compensate the timing skew. Since the calibration scheme depends on the digital output, all timing skew sources can be calibrated and the main ADC is maintained. The proposed scheme is effective within the entire frequency range of 0 ? fs/2. Compared with traditional calibration schemes, the proposed approach is more feasible and consumes significantly lesser power and smaller area.
基金supported by the National Natural Science Foundation of China(No.61006025)the Special Research Funds for Doctoral Program of Higher Education of China(No.20100071110026)
文摘A sampling switch with an embedded digital-to-skew converter(DSC) is presented.The proposed switch eliminates time-interleaved ADCs' skews by adjusting the boosted voltage.A similar bridged capacitors' charge sharing structure is used to minimize the area.The circuit is fabricated in a 0.18μm CMOS process and achieves sub-1 ps resolution and 200 ps timing range at a rate of 100 MS/s.The power consumption is 430μW at maximum.The measurement result also includes a 2-channel 14-bit 100 MS/s time-interleaved ADCs(TI-ADCs) with the proposed DSC switch's demonstration.This scheme is widely applicable for the clock skew and aperture error calibration demanded in TI-ADCs and SHA-less ADCs.
文摘为了解决传统双向DC/DC变换器的损耗较大和效率较低等实际问题,提出了一种将交错并联磁集成技术与软开关技术相结合的控制方法。首先,以三相交错并联磁集成双向DC/DC变换器为研究实例,分析了当变换器分别运行在一、二、三相电感时的3种工作状态。在每种状态下,分别讨论了电感反向电流的持续时间和死区时间,从而总结出了变换器运行在每种状态下可以实现零电压开关(zero voltage switch,ZVS)的条件。最后,通过实验进一步验证了理论分析的正确性,证实了该设计方案的实用性。
文摘提出了一种双通道可重构14 bit 125 MS/s流水线模数转换器(ADC).该双通道14 bit ADC可工作在并行双通道14 bit 125 MS/s、时间交织14 bit 250 MS/s以及求和15 bit 125 MS/s三种模式.为抑制通道间失配误差的影响,提出一种数模混合前台校准技术.为减少ADC输出端口数目,数据输出由高速串行数据发送器驱动,并且其工作模式有1.75,2,3.5 Gbit/s三种.该ADC电路采用0.18μm 1P5M 1.8 V CMOS工艺实现,测试结果表明,对于相同的10.1 MHz的输入信号,该ADC电路在14 bit 125 MS/s模式下的SNR和SFDR分别为72.5 dBFS和83.1dB,在14 bit 250 MS/s模式下的SNR和SFDR分别为71.3 dBFS和77.6 dB,在15 bit 125 MS/s模式下的SNR和SFDR分别为75.3 dBFS和87.4 dB.芯片总体功耗为461 mW,单通道ADC内核功耗为210 mW,面积为1.3×4 mm^2.
文摘提出了一种基于TMS320VC549定点DSP微处理器芯片的语音信号压缩/解压缩处理系统。该系统采用TLC320AD50C模数、数模转换器,采样率为8 kHz,处理能力为100 M IPS。系统配置有大容量存储器,具备资源扩展能力,适用于语音信号压缩/解压缩和语音识别、语音合成等其他领域。实验结果表明,系统对语音信号的压缩解压缩处理具有稳定性、灵活性和通用性。
