For an n-variable logic function,the power dissipation and area of the REED-MULLER （RM） circuit corresponding to each polarity are different. Based on the propagation algorithm of signal probability,the decompositio...For an n-variable logic function,the power dissipation and area of the REED-MULLER （RM） circuit corresponding to each polarity are different. Based on the propagation algorithm of signal probability,the decomposition algorithm of a multi-input XOR/AND gate,and the multiple segment algorithm of polarity conversion,this paper successfully applies the whole annealing genetic algorithm （WAGA） to find the best polarity of an RM circuit. Through testing eight large-scale circuits from the Microelectronics Center North Carolina （MCNC） Benchmark, the SYNOPSYS synthesis results show that the RM circuits corresponding to the best polarity found using the proposed algorithm attain average power,area,and max delay savings of 77.2% ,62.4% ,and 9.2% respectively,compared with those under polarity 0.展开更多
A quadrature mixer with a shared transconductor stage is analyzed,including voltage conversion gain, linearity, noise figure, and image rejection. The analysis indicates it has better performance than a conventional G...A quadrature mixer with a shared transconductor stage is analyzed,including voltage conversion gain, linearity, noise figure, and image rejection. The analysis indicates it has better performance than a conventional Gilbert mixer pair in commutating mode. A quadrature down-conversion mixer based on this topology is designed and optimized for an ultra high frequency RFID reader. Operating in the 915MHz ISM band, the presented quadrature mixer measures a conversion gain of 12.5dB,an IIP3 of 10dBm, an IIP2 of 58dBm, and an SSB noise figure of 17.6riB. The chip was fabricated in a 0. 18μm 1P6M RF CMOS process and consumes only 3mA of current from a 1.8V power supply.展开更多
For the high resolution required in a digital interface circuit of an accelerometer used in feeble gravity measurement, a switched-capacitor （SC） sigma-delta modulator （SDM） is proposed. Based on the principle and...For the high resolution required in a digital interface circuit of an accelerometer used in feeble gravity measurement, a switched-capacitor （SC） sigma-delta modulator （SDM） is proposed. Based on the principle and the topology structure of the SDMs, the influence of oversampling ratio, bits of an internal quantizer and the cascaded structure on weak signal detecting precision is analyzed, and an ideal low-distortion SDM with a second-order 1-bit structure satisfying the high- resolution interface circuit of an accelerometer is designed. With the research on non-idealities of each SDM block in the SC circuit implementation and their impacts on power consumption, the realized parameters of low-power SDMs based on different bandwidths are devised and the power consumption of each SDM is estimated. Time-domain behavioral simulation is explored based on Simulink. The results demonstrate that a 21- bit resolution of the designed SDMs can be achieved on the premise of low power, and the parameters for the circuit implementation can be directed to the transistor-level circuit design.展开更多
A novel operation mechanism of capacitorless SOl-DRAM （silicon on insulator dynamic random access memory） cell using impact ionization and GIDL （gated-induce drain leakage） effects for write ＂1＂ operation was pr...A novel operation mechanism of capacitorless SOl-DRAM （silicon on insulator dynamic random access memory） cell using impact ionization and GIDL （gated-induce drain leakage） effects for write ＂1＂ operation was proposed. The conventional capacitorless DRAM cell with single charge generating effect is either high speed or low power, while the proposed DG-FinFET （double-gate fin field effect transistor） cell employs the efficient integration of impact ionization and GIDL effects by coupling the front and back gates with optimal body doping profile and proper bias conditions, yielding high speed low power performance. The simulation results demonstrate ideal characteristics in both cell operations and power consumption. Low power consumption is achieved by using GIDL current at 0. luA when the coupling between the front and back gates restrains the impact ionization current in the first phase. The write operation of the cell is within Ins attributed to significant current of the impact ionization effect in the second phase. By shortening second phase, power consumption could be further decreased. The ratio of read ＂1＂ and read ＂0＂ current is more than 9.38E5. Moreover, the cell has great retention characteristics.展开更多
For applications requiring low-power,low-voltage and real-time,a novel analog VLSI implementation of continuous Marr wavelet transform based on CMOS log-domain integrator is proposed. Marr wavelet is approximated by a...For applications requiring low-power,low-voltage and real-time,a novel analog VLSI implementation of continuous Marr wavelet transform based on CMOS log-domain integrator is proposed. Marr wavelet is approximated by a parameterized class of function and with Levenbery-Marquardt nonlinear least square method,the optimum parameters of this function are obtained. The circuits of implementating Marr wavelet transform are composed of analog filter whose impulse response is the required wavelet. The filter design is based on IFLF structure with CMOS log-domain integrators as the main building blocks. SPICE simulations indicate an excellent approximations of ideal wavelet.展开更多
A new method of prefetching data blocks from the NVCache to the page cache in main memory and cascading prefetching n-blocks from a hard disk to the NVCache together was proposed to reduce the spin-up frequency of a h...A new method of prefetching data blocks from the NVCache to the page cache in main memory and cascading prefetching n-blocks from a hard disk to the NVCache together was proposed to reduce the spin-up frequency of a hybrid hard disk drive and thus enhance I/O performance.The proposed method consists of three steps:1) Analyzing the pattern of read requests in block units;2) Determining the number of blocks prefetched to the NVCache;3) Replacing blocks in the NVCache according to the block replacement policy.The proposed method can reduce the latency time of a hybrid hard disk and optimize the power consumption of an IPTV set-top box.Experimental results show that the proposed method provides better average response time compared to an existing adaptive multistream prefetching(AMP) method by 25.17%.It also reduces by 20.83% the average power consumption over that of the existing external caching in energy saving storage system(EXCES) method.展开更多
The seismic behaviors of an integral concreting frame, a light steel storey-adding frame and a storeyadding frame strengthened with carbon fiber reinforced polymer(CFRP)were investigated under low-cycle and repeated l...The seismic behaviors of an integral concreting frame, a light steel storey-adding frame and a storeyadding frame strengthened with carbon fiber reinforced polymer(CFRP)were investigated under low-cycle and repeated load(scale 1∶3). The failure characteristics, hysteretic behavior, rigidity degeneracy, deflection ductility and energy-dissipation capacity of the three specimens were compared. The test results reveal that chemicallybonded rebar technique can meet the requirements of storey-adding engineering. The carrying capacity, the deflection ductility, the energy-dissipating capacity and seismic performance of the light steel storey-adding frame are higher than those of the integral concreting frame, and they are the highest in the storey-adding frame strengthened with CFRP.展开更多
In this paper, by using the folding counter and linear feedback shift register, a new vector generator is proosed. The decisive testing patterns are generated by using the selected fold distance. Then the folding coun...In this paper, by using the folding counter and linear feedback shift register, a new vector generator is proosed. The decisive testing patterns are generated by using the selected fold distance. Then the folding counter seeds are encoded by the specialized seed encoder and clock gating, the ineffective patterns do not act upon the circuit under test, these testing patterns are designed to form a pseudo single input change set, so as to lead to prominent decreases in power consumption and redundant testing patterns generated by different seeds, without losing stuck-at fault coverage. Experimental results based on ISCAS＇85 benchmark circuits demonstrate the efficiency of the approach.展开更多
As feature size scales down, reliability issues like single event upset(SEU) have become serious for circuit and system designers, especially for those who work on memory and latch designs. In this paper, an improved ...As feature size scales down, reliability issues like single event upset(SEU) have become serious for circuit and system designers, especially for those who work on memory and latch designs. In this paper, an improved SEU tolerant data cell design based on the Quatro-10 T cell is proposed. The introduced cell enhances the capability of SEU tolerance by weakening the key transistors in the feedback loop to block the effects of transient fault. Simulation results show that our proposed design achieves obvious higher resilience to SEU and better performance on speed and power dissipation at the expense of an increased area. The proposed cell is a fully SEU immune design with an amount of critical charge at least 7 times more than the Quatro-10 T cell and has the lowest Power Delay Product. It shows that our design is very suitable in high-performance circuit and system design.展开更多
The ability to control magnetic vortex is critical for their potential applications in spintronic devices.Traditional methods including magnetic field,spin-polarized current etc.have been used to flip the core and/or ...The ability to control magnetic vortex is critical for their potential applications in spintronic devices.Traditional methods including magnetic field,spin-polarized current etc.have been used to flip the core and/or reverse circulation of vortex.However,it is challenging for deterministic electric-field control of the single magnetic vortex textures with time-reversal broken symmetry and no planar magnetic anisotropy.Here it is reported that a deterministic reversal of single magnetic vortex circulation can be driven back and forth by a space-varying strain in multiferroic heterostructures,which is controlled by using a bi-axial pulsed electric field.Phase-field simulation reveals the mechanism of the emerging magnetoelastic energy with the space variation and visualizes the reversal pathway of the vortex.This deterministic electric-field control of the single magnetic vortex textures demonstrates a new approach to integrate the low-dimensional spin texture into the magnetoelectric thin film devices with low energy consumption.展开更多
文摘For an n-variable logic function,the power dissipation and area of the REED-MULLER （RM） circuit corresponding to each polarity are different. Based on the propagation algorithm of signal probability,the decomposition algorithm of a multi-input XOR/AND gate,and the multiple segment algorithm of polarity conversion,this paper successfully applies the whole annealing genetic algorithm （WAGA） to find the best polarity of an RM circuit. Through testing eight large-scale circuits from the Microelectronics Center North Carolina （MCNC） Benchmark, the SYNOPSYS synthesis results show that the RM circuits corresponding to the best polarity found using the proposed algorithm attain average power,area,and max delay savings of 77.2% ,62.4% ,and 9.2% respectively,compared with those under polarity 0.
文摘A quadrature mixer with a shared transconductor stage is analyzed,including voltage conversion gain, linearity, noise figure, and image rejection. The analysis indicates it has better performance than a conventional Gilbert mixer pair in commutating mode. A quadrature down-conversion mixer based on this topology is designed and optimized for an ultra high frequency RFID reader. Operating in the 915MHz ISM band, the presented quadrature mixer measures a conversion gain of 12.5dB,an IIP3 of 10dBm, an IIP2 of 58dBm, and an SSB noise figure of 17.6riB. The chip was fabricated in a 0. 18μm 1P6M RF CMOS process and consumes only 3mA of current from a 1.8V power supply.
基金The National High Technology Research and Development Program of China (863 Program) ( No. 2006AA12Z302)
文摘For the high resolution required in a digital interface circuit of an accelerometer used in feeble gravity measurement, a switched-capacitor （SC） sigma-delta modulator （SDM） is proposed. Based on the principle and the topology structure of the SDMs, the influence of oversampling ratio, bits of an internal quantizer and the cascaded structure on weak signal detecting precision is analyzed, and an ideal low-distortion SDM with a second-order 1-bit structure satisfying the high- resolution interface circuit of an accelerometer is designed. With the research on non-idealities of each SDM block in the SC circuit implementation and their impacts on power consumption, the realized parameters of low-power SDMs based on different bandwidths are devised and the power consumption of each SDM is estimated. Time-domain behavioral simulation is explored based on Simulink. The results demonstrate that a 21- bit resolution of the designed SDMs can be achieved on the premise of low power, and the parameters for the circuit implementation can be directed to the transistor-level circuit design.
文摘A novel operation mechanism of capacitorless SOl-DRAM （silicon on insulator dynamic random access memory） cell using impact ionization and GIDL （gated-induce drain leakage） effects for write ＂1＂ operation was proposed. The conventional capacitorless DRAM cell with single charge generating effect is either high speed or low power, while the proposed DG-FinFET （double-gate fin field effect transistor） cell employs the efficient integration of impact ionization and GIDL effects by coupling the front and back gates with optimal body doping profile and proper bias conditions, yielding high speed low power performance. The simulation results demonstrate ideal characteristics in both cell operations and power consumption. Low power consumption is achieved by using GIDL current at 0. luA when the coupling between the front and back gates restrains the impact ionization current in the first phase. The write operation of the cell is within Ins attributed to significant current of the impact ionization effect in the second phase. By shortening second phase, power consumption could be further decreased. The ratio of read ＂1＂ and read ＂0＂ current is more than 9.38E5. Moreover, the cell has great retention characteristics.
文摘For applications requiring low-power,low-voltage and real-time,a novel analog VLSI implementation of continuous Marr wavelet transform based on CMOS log-domain integrator is proposed. Marr wavelet is approximated by a parameterized class of function and with Levenbery-Marquardt nonlinear least square method,the optimum parameters of this function are obtained. The circuits of implementating Marr wavelet transform are composed of analog filter whose impulse response is the required wavelet. The filter design is based on IFLF structure with CMOS log-domain integrators as the main building blocks. SPICE simulations indicate an excellent approximations of ideal wavelet.
基金supported in part by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (2011-0004114)in part by the Ministry of Knowledge Economy (MKE) and Korea Institute for Advancement in Technology (KIAT) through the Workforce Development Program in Strategic Technology in part by the MKE (The Ministry of Knowledge Economy), Korea, under the CITRC (Convergence Information Technology Research Center) support program (NIPA-2012-C6150-1201-0001) supervised by the NIPA (National IT Industry Promotion Agency)
文摘A new method of prefetching data blocks from the NVCache to the page cache in main memory and cascading prefetching n-blocks from a hard disk to the NVCache together was proposed to reduce the spin-up frequency of a hybrid hard disk drive and thus enhance I/O performance.The proposed method consists of three steps:1) Analyzing the pattern of read requests in block units;2) Determining the number of blocks prefetched to the NVCache;3) Replacing blocks in the NVCache according to the block replacement policy.The proposed method can reduce the latency time of a hybrid hard disk and optimize the power consumption of an IPTV set-top box.Experimental results show that the proposed method provides better average response time compared to an existing adaptive multistream prefetching(AMP) method by 25.17%.It also reduces by 20.83% the average power consumption over that of the existing external caching in energy saving storage system(EXCES) method.
基金Supported by the National Natural Science Foundation of China(No.51379142)
文摘The seismic behaviors of an integral concreting frame, a light steel storey-adding frame and a storeyadding frame strengthened with carbon fiber reinforced polymer(CFRP)were investigated under low-cycle and repeated load(scale 1∶3). The failure characteristics, hysteretic behavior, rigidity degeneracy, deflection ductility and energy-dissipation capacity of the three specimens were compared. The test results reveal that chemicallybonded rebar technique can meet the requirements of storey-adding engineering. The carrying capacity, the deflection ductility, the energy-dissipating capacity and seismic performance of the light steel storey-adding frame are higher than those of the integral concreting frame, and they are the highest in the storey-adding frame strengthened with CFRP.
基金supported by General Equipments Ministry for the Fore-research of Military Electronic Devices Technology in the 11th Five Plan(No.51323030406)
文摘In this paper, by using the folding counter and linear feedback shift register, a new vector generator is proosed. The decisive testing patterns are generated by using the selected fold distance. Then the folding counter seeds are encoded by the specialized seed encoder and clock gating, the ineffective patterns do not act upon the circuit under test, these testing patterns are designed to form a pseudo single input change set, so as to lead to prominent decreases in power consumption and redundant testing patterns generated by different seeds, without losing stuck-at fault coverage. Experimental results based on ISCAS＇85 benchmark circuits demonstrate the efficiency of the approach.
基金supported by the Fundamental Research Funds for the Central Universitiesthe National Natural Science Foundation of China for the Youth(Grant No.61306111)
文摘As feature size scales down, reliability issues like single event upset(SEU) have become serious for circuit and system designers, especially for those who work on memory and latch designs. In this paper, an improved SEU tolerant data cell design based on the Quatro-10 T cell is proposed. The introduced cell enhances the capability of SEU tolerance by weakening the key transistors in the feedback loop to block the effects of transient fault. Simulation results show that our proposed design achieves obvious higher resilience to SEU and better performance on speed and power dissipation at the expense of an increased area. The proposed cell is a fully SEU immune design with an amount of critical charge at least 7 times more than the Quatro-10 T cell and has the lowest Power Delay Product. It shows that our design is very suitable in high-performance circuit and system design.
基金supported by the National Key Research and Development Program of China(2016YFA0302300 and 2017YFA0206200)Basic Science Center Program of the National Natural Science Foundation of China(51788104)+5 种基金National Natural Science Foundation of China(11974052,51972028)Beijing Natural Science Foundation(Z190008)Chinese Academy of Sciences Interdisciplinary Innovation Teamfunded by the Director,Office of Science,Office of Basic Energy Sciences,Materials Science and Engineering Department of the US Department of Energy(DOE)in the Quantum Materials Program(KC2202)under Contract No.DEAC02-05CH11231the support by the Science Alliance Joint Directed Research&Development Programthe Transdisciplinary Academy Program at the University of Tennessee。
文摘The ability to control magnetic vortex is critical for their potential applications in spintronic devices.Traditional methods including magnetic field,spin-polarized current etc.have been used to flip the core and/or reverse circulation of vortex.However,it is challenging for deterministic electric-field control of the single magnetic vortex textures with time-reversal broken symmetry and no planar magnetic anisotropy.Here it is reported that a deterministic reversal of single magnetic vortex circulation can be driven back and forth by a space-varying strain in multiferroic heterostructures,which is controlled by using a bi-axial pulsed electric field.Phase-field simulation reveals the mechanism of the emerging magnetoelastic energy with the space variation and visualizes the reversal pathway of the vortex.This deterministic electric-field control of the single magnetic vortex textures demonstrates a new approach to integrate the low-dimensional spin texture into the magnetoelectric thin film devices with low energy consumption.
