A runtime reconfigurable very-large-scale integration （VLSI） architecture for image and video scaling by arbitrary factors with good antialiasing performance is presented in this paper. Video scal- ing is used in a ...A runtime reconfigurable very-large-scale integration （VLSI） architecture for image and video scaling by arbitrary factors with good antialiasing performance is presented in this paper. Video scal- ing is used in a wide range of applications from broadcast, medical imaging and high-resolution video effects to video surveillance, and video conferencing. Many algorithms have been proposed for these applications, such as piecewise polynomial kernels and windowed sinc kernels. The sum of three shifted versions of a B-spline function, whose weights can be adjusted for different applications, is adopted as the main filter. The proposed algorithm is confirmed to be effective on image scaling ap- plications and also verified by many widely acknowledged image quality measures. The reconfigu- rable hardware architecture constitutes an arbitrary scaler with low resource consumption and high performance targeted for field programmable gate array （FPGA） devices. The scaling factor can be changed on-the-fly, and the filter can also be changed during runtime within a unifying framework.展开更多
With the scaling development of the minimum lithographic size,the scaling trend of CMOS imager pixel size and fill factor has been computed according to the Moore rule.When the CMOS minimum lithographic feature scales...With the scaling development of the minimum lithographic size,the scaling trend of CMOS imager pixel size and fill factor has been computed according to the Moore rule.When the CMOS minimum lithographic feature scales down to 0.35 μm,the CCD image pixel size is not so easy to be reduced and but the CMOS image pixel size benefits from the scaling minimum lithographic feature. However, when the CMOS technology is downscaled to or under 0.35 μm,the fabrication of CMOS image sensors will be limited by the standard CMOS process in both ways of shallow trench isolation and source/drain junction,which results in pixel crosstalk.The impact of the crosstalk on the active pixel CMOS image sensor is analyzed based on the technology scaling.Some suppressed crosstalk methods have been reviewed.The best way is that combining the advantages of CMOS and SOI technology to fabricate the image sensors will reduce the pixel crosstalk.展开更多
基金Supported by the National Natural Science Foundation of China(No.60972126)the Joint Funds of the National Natural Science Foundation of China(No.U0935002/L05)+1 种基金the Beijing Municipal Natural Science Foundation(No.4102060)the State Key Program of the National Natural Science of China(No.61032007)
文摘A runtime reconfigurable very-large-scale integration （VLSI） architecture for image and video scaling by arbitrary factors with good antialiasing performance is presented in this paper. Video scal- ing is used in a wide range of applications from broadcast, medical imaging and high-resolution video effects to video surveillance, and video conferencing. Many algorithms have been proposed for these applications, such as piecewise polynomial kernels and windowed sinc kernels. The sum of three shifted versions of a B-spline function, whose weights can be adjusted for different applications, is adopted as the main filter. The proposed algorithm is confirmed to be effective on image scaling ap- plications and also verified by many widely acknowledged image quality measures. The reconfigu- rable hardware architecture constitutes an arbitrary scaler with low resource consumption and high performance targeted for field programmable gate array （FPGA） devices. The scaling factor can be changed on-the-fly, and the filter can also be changed during runtime within a unifying framework.
文摘With the scaling development of the minimum lithographic size,the scaling trend of CMOS imager pixel size and fill factor has been computed according to the Moore rule.When the CMOS minimum lithographic feature scales down to 0.35 μm,the CCD image pixel size is not so easy to be reduced and but the CMOS image pixel size benefits from the scaling minimum lithographic feature. However, when the CMOS technology is downscaled to or under 0.35 μm,the fabrication of CMOS image sensors will be limited by the standard CMOS process in both ways of shallow trench isolation and source/drain junction,which results in pixel crosstalk.The impact of the crosstalk on the active pixel CMOS image sensor is analyzed based on the technology scaling.Some suppressed crosstalk methods have been reviewed.The best way is that combining the advantages of CMOS and SOI technology to fabricate the image sensors will reduce the pixel crosstalk.
