相较于传统注入式同步无线电能和数据传输(Simultaneous Wireless Power and Data Transfer,SWPDT),“共口径”SWPDT方案具有电能传输功率大、转换效率高、数据传输速率高、可靠性好的优点。针对共口径集成后高压大功率电能传输通道与...相较于传统注入式同步无线电能和数据传输(Simultaneous Wireless Power and Data Transfer,SWPDT),“共口径”SWPDT方案具有电能传输功率大、转换效率高、数据传输速率高、可靠性好的优点。针对共口径集成后高压大功率电能传输通道与通信链路强耦合导致通信速率下降乃至失败的问题,结合D型传能松耦合变压器,提出基于耦合电感的双边LCC拓扑、DD型通信线圈及滤波网络协同设计的解耦设计技术,实现传能线圈谐波优化和电能-通信空域解耦,提升了通信链路通带阻抗匹配和带外抑制能力,增强了与传能线圈的频域解耦。分析了功率传输链路和数据传输链路的设计及解耦实现原理,构建了一台270 V输入、270 V/3 kW恒压输出、传能30 mm的SWPDT原理样机。实验结果证明了所提解耦设计技术的可行性和先进性,在实现94.89%电能转换效率的同时可实现50 Mb/s的高速数据同步传输。展开更多
In recent years the variety and complexity of Wireless Sensor Network （WSN） applications, the nodes and the functions they are expected to perform have increased immensely. This poses the question of reducing the ti...In recent years the variety and complexity of Wireless Sensor Network （WSN） applications, the nodes and the functions they are expected to perform have increased immensely. This poses the question of reducing the time from initial design of WSN applications to their implementation as a major research topic. RF communication programs for WSN nodes are generally written on microcontroller units （MCUs） for universal asynchronous receiver/transmitter （UART） data communication, however nowadays radio frequency （RF） designs based on field-programmable gate array （FPGA） have emerged as a very powerful alternative, due to their parallel data processing ability and software reconfigurability. In this paper, the authors present a prototype of a flexible multi-node transceiver and monitoring system. The prototype is designed for time-critical applications and can be also reconfigured for other applications like event tracking. The processing power of FPGA is combined with a simple communication protocol. The system consists of three major parts： wireless nodes, the FPGA and display used for visualization of data processing. The transmission protocol is based on preamble and synchronous data transmission, where the receiver adjusts the receiving baud rate in the range from min. 300 to max. 2400 bps. The most important contribution of this work is using the virtual PicoBlaze Soft-Core Processor for controlling the data transmission through the RF modules. The proposed system has been evaluated based on logic utilization, in terms of the number of slice flip flops, the number of 4 input LUTs （Look-Up Tables） and the number of bonded lOBs （Input Output Blocks）. The results for capacity usage are very promising as compared to other similar research.展开更多
文摘相较于传统注入式同步无线电能和数据传输(Simultaneous Wireless Power and Data Transfer,SWPDT),“共口径”SWPDT方案具有电能传输功率大、转换效率高、数据传输速率高、可靠性好的优点。针对共口径集成后高压大功率电能传输通道与通信链路强耦合导致通信速率下降乃至失败的问题,结合D型传能松耦合变压器,提出基于耦合电感的双边LCC拓扑、DD型通信线圈及滤波网络协同设计的解耦设计技术,实现传能线圈谐波优化和电能-通信空域解耦,提升了通信链路通带阻抗匹配和带外抑制能力,增强了与传能线圈的频域解耦。分析了功率传输链路和数据传输链路的设计及解耦实现原理,构建了一台270 V输入、270 V/3 kW恒压输出、传能30 mm的SWPDT原理样机。实验结果证明了所提解耦设计技术的可行性和先进性,在实现94.89%电能转换效率的同时可实现50 Mb/s的高速数据同步传输。
文摘In recent years the variety and complexity of Wireless Sensor Network （WSN） applications, the nodes and the functions they are expected to perform have increased immensely. This poses the question of reducing the time from initial design of WSN applications to their implementation as a major research topic. RF communication programs for WSN nodes are generally written on microcontroller units （MCUs） for universal asynchronous receiver/transmitter （UART） data communication, however nowadays radio frequency （RF） designs based on field-programmable gate array （FPGA） have emerged as a very powerful alternative, due to their parallel data processing ability and software reconfigurability. In this paper, the authors present a prototype of a flexible multi-node transceiver and monitoring system. The prototype is designed for time-critical applications and can be also reconfigured for other applications like event tracking. The processing power of FPGA is combined with a simple communication protocol. The system consists of three major parts： wireless nodes, the FPGA and display used for visualization of data processing. The transmission protocol is based on preamble and synchronous data transmission, where the receiver adjusts the receiving baud rate in the range from min. 300 to max. 2400 bps. The most important contribution of this work is using the virtual PicoBlaze Soft-Core Processor for controlling the data transmission through the RF modules. The proposed system has been evaluated based on logic utilization, in terms of the number of slice flip flops, the number of 4 input LUTs （Look-Up Tables） and the number of bonded lOBs （Input Output Blocks）. The results for capacity usage are very promising as compared to other similar research.
