The design and implementation of a novel ADC architecture called ring-ADC for digital voltage regulator module controllers are presented. Based on the principle of voltage-controlled oscillators＇ transform from volta...The design and implementation of a novel ADC architecture called ring-ADC for digital voltage regulator module controllers are presented. Based on the principle of voltage-controlled oscillators＇ transform from voltage to frequency,the A/D conversion of ring-ADC achieves good linearity and precise calibration against process variations compared with the delay-line ADC. A differential pulse counting discriminator also helps decrease the power consumption of the ring-ADC. It is fabricated with a Chartered 0.35μm CMOS process, and the measurement results of the integral and differential nonlinearity performance are 0.92LSB and 1.2LSB respectively. The maximum gain error measured in ten sample chips is ± 3.85%. With sampling rate of 500kHz and when the voltage regulator module （VRM） works in steady state, the ring-ADC＇s average power consumption is 2.56mW. The ring-ADC is verified to meet the requirements for digital VRM controller application.展开更多
A 2.4GHz monolithic CMOS receiver with direct-conversion architecture is presented. This quadrature receiver is designed for 802.11b wireless LAN applications at the maximum data rate of 11Mbps as a low-cost solution....A 2.4GHz monolithic CMOS receiver with direct-conversion architecture is presented. This quadrature receiver is designed for 802.11b wireless LAN applications at the maximum data rate of 11Mbps as a low-cost solution. Five key blocks,i, e., a low noise amplifier （LNA）, a down-conversion mixer, a variable gain amplifier, a low pass filter, and a DC- offset cancellation circuit,are designed based on system design and low noise high linearity considerations. The necessary auxiliary circuits are also included. Fabricated in SMIC 0.18μm 1p6m RF CMOS process, the receiver＇s performance is measured as：4. 1 dB noise figure, - 7.5dBm input third order intercept point （IIP3） for LNA ＆ mixer at high gain setting, - 14dBm IIP3 for the whole receiver,53dBc @30MHz offset of adjacent channel power rejection,and less than 5mV out- put DC-offset. The receiver consumes 44mA under a 1.8V power supply with I,Q two paths.展开更多
A design of a linear and fully-balanced operational transconductanee amplifier （OTA） with improved high DC gain and wide bandwidth is presented. Derivative from a single common-source field effect transistor （FET）...A design of a linear and fully-balanced operational transconductanee amplifier （OTA） with improved high DC gain and wide bandwidth is presented. Derivative from a single common-source field effect transistor （FET） cas- cade and its DC I-V characteristics,the third-order coefficient g3 hasbeen well compensated with a parallel FET operated in the triode region, which has even-odd symmetries between the boundary of the saturation and triode region. Therefore,for high linearity,a simple solution is obtained to increase input signal amplitude in saturation for the application of OTA continuous-time filters. A negative resistance load （NRL） technique is used for the compensation of parasitic output resistance and an achievement of a high DC-gain of the OTA circuits without extra internal nodes. Additionally, derivations from the ideal -90° phase of the gm-C integrator mainly due to a finite DC gain and parasitic poles will be avoided in the frequency range of interest. HSPICE simulation shows that the total harmonic distortion at 1Vp-p is less than 1% from a single 3.3V supply. As an application of the VHF CMOS OTA,a second-order OTA-C bandpass filter is fabricated using a 0. 18μm CMOS process with two kinds of gate-oxide layers, which has achieved a center frequency of 20MHz,a 3dB-bandwidth of 180kHz,and a quality factor of 110.展开更多
文摘The design and implementation of a novel ADC architecture called ring-ADC for digital voltage regulator module controllers are presented. Based on the principle of voltage-controlled oscillators＇ transform from voltage to frequency,the A/D conversion of ring-ADC achieves good linearity and precise calibration against process variations compared with the delay-line ADC. A differential pulse counting discriminator also helps decrease the power consumption of the ring-ADC. It is fabricated with a Chartered 0.35μm CMOS process, and the measurement results of the integral and differential nonlinearity performance are 0.92LSB and 1.2LSB respectively. The maximum gain error measured in ten sample chips is ± 3.85%. With sampling rate of 500kHz and when the voltage regulator module （VRM） works in steady state, the ring-ADC＇s average power consumption is 2.56mW. The ring-ADC is verified to meet the requirements for digital VRM controller application.
基金the National Natural Science Foundation of China(No.60606009)~~
文摘A 2.4GHz monolithic CMOS receiver with direct-conversion architecture is presented. This quadrature receiver is designed for 802.11b wireless LAN applications at the maximum data rate of 11Mbps as a low-cost solution. Five key blocks,i, e., a low noise amplifier （LNA）, a down-conversion mixer, a variable gain amplifier, a low pass filter, and a DC- offset cancellation circuit,are designed based on system design and low noise high linearity considerations. The necessary auxiliary circuits are also included. Fabricated in SMIC 0.18μm 1p6m RF CMOS process, the receiver＇s performance is measured as：4. 1 dB noise figure, - 7.5dBm input third order intercept point （IIP3） for LNA ＆ mixer at high gain setting, - 14dBm IIP3 for the whole receiver,53dBc @30MHz offset of adjacent channel power rejection,and less than 5mV out- put DC-offset. The receiver consumes 44mA under a 1.8V power supply with I,Q two paths.
文摘A design of a linear and fully-balanced operational transconductanee amplifier （OTA） with improved high DC gain and wide bandwidth is presented. Derivative from a single common-source field effect transistor （FET） cas- cade and its DC I-V characteristics,the third-order coefficient g3 hasbeen well compensated with a parallel FET operated in the triode region, which has even-odd symmetries between the boundary of the saturation and triode region. Therefore,for high linearity,a simple solution is obtained to increase input signal amplitude in saturation for the application of OTA continuous-time filters. A negative resistance load （NRL） technique is used for the compensation of parasitic output resistance and an achievement of a high DC-gain of the OTA circuits without extra internal nodes. Additionally, derivations from the ideal -90° phase of the gm-C integrator mainly due to a finite DC gain and parasitic poles will be avoided in the frequency range of interest. HSPICE simulation shows that the total harmonic distortion at 1Vp-p is less than 1% from a single 3.3V supply. As an application of the VHF CMOS OTA,a second-order OTA-C bandpass filter is fabricated using a 0. 18μm CMOS process with two kinds of gate-oxide layers, which has achieved a center frequency of 20MHz,a 3dB-bandwidth of 180kHz,and a quality factor of 110.
