Electrical properties of high quality ultra thin nitride/oxynitride(N/O)stack dielectrics pMOS capacitor with refractory metal gate electrode are investigated,and ultra thin (<2 nm) N/O stack gate dielectrics with ...Electrical properties of high quality ultra thin nitride/oxynitride(N/O)stack dielectrics pMOS capacitor with refractory metal gate electrode are investigated,and ultra thin (<2 nm) N/O stack gate dielectrics with significant low leakage current and high resistance to boron penetration are fabricated.Experiment results show that the stack gate dielectric of nitride/oxynitride combined with improved sputtered tungsten/titanium nitride (W/TiN) gate electrode is one of the candidates for deep sub-micron metal gate CMOS devices.展开更多
By complementing the equivalent oxide thickness （EOT） of a 1.7nm nitride/oxynitride （N/O） stack gate dielectric （EOT- 1.7nm） with a W/TiN metal gate electrode,metal gate CMOS devices with sub-100nm gate length a...By complementing the equivalent oxide thickness （EOT） of a 1.7nm nitride/oxynitride （N/O） stack gate dielectric （EOT- 1.7nm） with a W/TiN metal gate electrode,metal gate CMOS devices with sub-100nm gate length are fabricated in China for the first time. The key technologies adopted to restrain SCE and to improve drive ability include a 1.7nm N/O stack gate dielectric, non-CMP planarization technology, a T-type refractory W/TiN metal stack gate electrode, and a novel super steep retrograde channel doping using heavy ion implantation and a double sidewall scheme. Using these optimized key technologies, high performance 95nm metal gate CMOS devices with excellent SCE and good driving ability are fabricated. Under power supply voltages of VDS ± 1.5V and VGS± 1.8V,drive currents of 679μA/μm for nMOS and - 327μA/μm for pMOS are obtained. A subthreshold slope of 84.46mV/dec, DIBL of 34.76mV/V, and Vth of 0.26V for nMOS, and a subthreshold slope of 107.4mV/dec,DIBL of 54.46mV/V, and Vth of 0.27V for pMOS are achieved. These results show that the combined technology has indeed thoroughly eliminated the boron penetration phenomenon and polysilicon depletion effect ,effectively reduced gate tunneling leakage, and improved device reliability.展开更多
Datong-Qinhuangdao line, as the first electrified double-track heavy-haul line dedicated to coal transport in China, extends from Datong in the west, and reaches Qinhuangdao in the east, opened to traffic in December,...Datong-Qinhuangdao line, as the first electrified double-track heavy-haul line dedicated to coal transport in China, extends from Datong in the west, and reaches Qinhuangdao in the east, opened to traffic in December, 1992, totaling 653 km with the designed annual traffic volume of 1×108 t. In order to meet the demands of national economic development, the transport capacity of the line must be enhanced greatly. Depending on independent innovation, MOR, for the first time in the world,realizes the integration between GSM-R and Locotrol, the integration between 800 MHz digital radio and Locotrol, and the integration between a single set of Locotrol and SS4 locomotive. Meanwhile, CR develops equipment portfolio for heavy-haul through combining 2 high power locomotives of HXD series (means harmony) with controllable EOT. Relying on integration and innovation, it succeeds in operating 20 kt-level combined heavy-haul train on Datong-Qinhuangdao line, which tripled the annual traffic volume of the line from 1×108 t in 2002 to 3×108 t in 2007.展开更多
In this paper, we report the fabrication, electrical and physical characteristics of TiN/HfO2/Si MOS capacitors with erbium （Er） ion implantation. It is demonstrated that the fiat band voltage can be reduced by 0.4 ...In this paper, we report the fabrication, electrical and physical characteristics of TiN/HfO2/Si MOS capacitors with erbium （Er） ion implantation. It is demonstrated that the fiat band voltage can be reduced by 0.4 V due to the formation of Er oxide. Moreover, it is observed that the equivalent oxide thickness is thinned down by 0.5 nm because the thickness of interfacial layer is significantly reduced, which is thought to be attributed to the strong binding capability of the implanted Er atoms with oxygen atoms. In addition, cross-sectional transmission electron microscopy experiment shows that the HfO2 layer with Er ion implantation is still amorphous after annealing at a high temperature. This Er ion implantation technique has the potential to be implemented as a band edge metal gate solution for NMOS without a capping layer, and may also satisfy the demand of the EOT reduction in 32 nm technology node.展开更多
Transistor size is constantly being reduced to improve performance as well as power consumption. For the channel length to be reduced, the corresponding gate dielectric thickness should also be reduced. Unfortunately,...Transistor size is constantly being reduced to improve performance as well as power consumption. For the channel length to be reduced, the corresponding gate dielectric thickness should also be reduced. Unfortunately, graphene devices are more complicated due to an extra capacitance called quantum capacitance （CQ） which limits the effective gate dielectric reduction. In this work, we analyzed the effect of CQ on device-scaling issues by extracting it from scaling of the channel length of devices. In contrast to previous reports for metal-insulator- metal structures, a practical device structure was used in conjunction with direct radio-frequency field-effect transistor measurements to describe the graphene channels. In order to precisely extract device parameters, we reassessed the equivalent circuit, and concluded that the on-state model should in fact be used. By careful consideration of the underlap region, our device modeling was shown to be in good agreement with the experimental data. CQ contributions to equivalent oxide thickness were analyzed in detail for varying impurity concentrations in graphene. Finally, we were able to demonstrate that despite contributions from CQ, graphene＇s high mobility and low-voltage operation allows for ~raphene channels suitable for next generation transistors.展开更多
文摘Electrical properties of high quality ultra thin nitride/oxynitride(N/O)stack dielectrics pMOS capacitor with refractory metal gate electrode are investigated,and ultra thin (<2 nm) N/O stack gate dielectrics with significant low leakage current and high resistance to boron penetration are fabricated.Experiment results show that the stack gate dielectric of nitride/oxynitride combined with improved sputtered tungsten/titanium nitride (W/TiN) gate electrode is one of the candidates for deep sub-micron metal gate CMOS devices.
文摘By complementing the equivalent oxide thickness （EOT） of a 1.7nm nitride/oxynitride （N/O） stack gate dielectric （EOT- 1.7nm） with a W/TiN metal gate electrode,metal gate CMOS devices with sub-100nm gate length are fabricated in China for the first time. The key technologies adopted to restrain SCE and to improve drive ability include a 1.7nm N/O stack gate dielectric, non-CMP planarization technology, a T-type refractory W/TiN metal stack gate electrode, and a novel super steep retrograde channel doping using heavy ion implantation and a double sidewall scheme. Using these optimized key technologies, high performance 95nm metal gate CMOS devices with excellent SCE and good driving ability are fabricated. Under power supply voltages of VDS ± 1.5V and VGS± 1.8V,drive currents of 679μA/μm for nMOS and - 327μA/μm for pMOS are obtained. A subthreshold slope of 84.46mV/dec, DIBL of 34.76mV/V, and Vth of 0.26V for nMOS, and a subthreshold slope of 107.4mV/dec,DIBL of 54.46mV/V, and Vth of 0.27V for pMOS are achieved. These results show that the combined technology has indeed thoroughly eliminated the boron penetration phenomenon and polysilicon depletion effect ,effectively reduced gate tunneling leakage, and improved device reliability.
文摘Datong-Qinhuangdao line, as the first electrified double-track heavy-haul line dedicated to coal transport in China, extends from Datong in the west, and reaches Qinhuangdao in the east, opened to traffic in December, 1992, totaling 653 km with the designed annual traffic volume of 1×108 t. In order to meet the demands of national economic development, the transport capacity of the line must be enhanced greatly. Depending on independent innovation, MOR, for the first time in the world,realizes the integration between GSM-R and Locotrol, the integration between 800 MHz digital radio and Locotrol, and the integration between a single set of Locotrol and SS4 locomotive. Meanwhile, CR develops equipment portfolio for heavy-haul through combining 2 high power locomotives of HXD series (means harmony) with controllable EOT. Relying on integration and innovation, it succeeds in operating 20 kt-level combined heavy-haul train on Datong-Qinhuangdao line, which tripled the annual traffic volume of the line from 1×108 t in 2002 to 3×108 t in 2007.
基金supported by the State Key Development Program for Basic Research of China(Grant No. 2011CBA00602)the National Natural Science Foundation of China(Grant Nos. 60876076 and 60976013)
文摘In this paper, we report the fabrication, electrical and physical characteristics of TiN/HfO2/Si MOS capacitors with erbium （Er） ion implantation. It is demonstrated that the fiat band voltage can be reduced by 0.4 V due to the formation of Er oxide. Moreover, it is observed that the equivalent oxide thickness is thinned down by 0.5 nm because the thickness of interfacial layer is significantly reduced, which is thought to be attributed to the strong binding capability of the implanted Er atoms with oxygen atoms. In addition, cross-sectional transmission electron microscopy experiment shows that the HfO2 layer with Er ion implantation is still amorphous after annealing at a high temperature. This Er ion implantation technique has the potential to be implemented as a band edge metal gate solution for NMOS without a capping layer, and may also satisfy the demand of the EOT reduction in 32 nm technology node.
文摘Transistor size is constantly being reduced to improve performance as well as power consumption. For the channel length to be reduced, the corresponding gate dielectric thickness should also be reduced. Unfortunately, graphene devices are more complicated due to an extra capacitance called quantum capacitance （CQ） which limits the effective gate dielectric reduction. In this work, we analyzed the effect of CQ on device-scaling issues by extracting it from scaling of the channel length of devices. In contrast to previous reports for metal-insulator- metal structures, a practical device structure was used in conjunction with direct radio-frequency field-effect transistor measurements to describe the graphene channels. In order to precisely extract device parameters, we reassessed the equivalent circuit, and concluded that the on-state model should in fact be used. By careful consideration of the underlap region, our device modeling was shown to be in good agreement with the experimental data. CQ contributions to equivalent oxide thickness were analyzed in detail for varying impurity concentrations in graphene. Finally, we were able to demonstrate that despite contributions from CQ, graphene＇s high mobility and low-voltage operation allows for ~raphene channels suitable for next generation transistors.
