Y2000-62096-143 0010936体 CMOS 集成电路封锁保护用的提取简单布图规则的新试验法=New experimental methodology to extractcompact layout rules for latch prevention in bulk CMOSIC’s[会,英]/Ker,M.-D.& Lo,W.-Y.//Proceed-...Y2000-62096-143 0010936体 CMOS 集成电路封锁保护用的提取简单布图规则的新试验法=New experimental methodology to extractcompact layout rules for latch prevention in bulk CMOSIC’s[会,英]/Ker,M.-D.& Lo,W.-Y.//Proceed-ings of the IEEE 1999 Custom Integrated Circuits Con-ference.—143～146(UC)Y2000-62096-277 0010937高性能低功率用的定制电路技术(收录论文6篇)=Session 13:custom circuit techniques for high perfor-mance and low-power applications[会。展开更多
文摘Y2000-62096-143 0010936体 CMOS 集成电路封锁保护用的提取简单布图规则的新试验法=New experimental methodology to extractcompact layout rules for latch prevention in bulk CMOSIC’s[会,英]/Ker,M.-D.& Lo,W.-Y.//Proceed-ings of the IEEE 1999 Custom Integrated Circuits Con-ference.—143～146(UC)Y2000-62096-277 0010937高性能低功率用的定制电路技术(收录论文6篇)=Session 13:custom circuit techniques for high perfor-mance and low-power applications[会。
