The hardware optimization technique of mono similarity system generation is presented based on hardware/software(HW/SW) co design.First,the coarse structure of sub graphs' matching based on full customized HW...The hardware optimization technique of mono similarity system generation is presented based on hardware/software(HW/SW) co design.First,the coarse structure of sub graphs' matching based on full customized HW/SW co design is put forward.Then,a universal sub graphs' combination method is discussed.Next,a more advanced vertexes' compression algorithm based on sub graphs' combination method is discussed with great emphasis.Experiments are done successfully with perfect results verifying all the formulas and the methods above.展开更多
Based on the characteristics of ATM system and the special requirement of financial transaction, an overall design of hardware and software structure of ATM was made. For software structure, the pattern of modules and...Based on the characteristics of ATM system and the special requirement of financial transaction, an overall design of hardware and software structure of ATM was made. For software structure, the pattern of modules and table? drive is adopted to realize the security of financial transaction and the diagnosis of communication fault. A new method, which is based on the application layer, transport layer and network layer, is used for diagnosing communication fault. Supporting both magnetic card and IC card, the system has been put into use in real financial systems, and has brought about both economic and social effects.展开更多
A hardware/software field programmable gate array （FPGA）-based driver system was proposed and demonstrated for the KAF-39000 large area high resolution charge coupled device （CCD）. The requirements of the KAF-3900...A hardware/software field programmable gate array （FPGA）-based driver system was proposed and demonstrated for the KAF-39000 large area high resolution charge coupled device （CCD）. The requirements of the KAF-39000 driver system were analyzed. The structure of ＂microprocessor with application specific integrated circuit （ASIC） chips＂ was implemented to design the driver system. The system test results showed that dual channels of imaging analog data were obtained with a frame rate of 0.87frame/s. The frequencies of horizontal timing and vertical timing were 22.9MHz and 28.7kHz, respectively, which almost reached the theoretical value of 24 MHz and 30kHz, respectively.展开更多
文摘The hardware optimization technique of mono similarity system generation is presented based on hardware/software(HW/SW) co design.First,the coarse structure of sub graphs' matching based on full customized HW/SW co design is put forward.Then,a universal sub graphs' combination method is discussed.Next,a more advanced vertexes' compression algorithm based on sub graphs' combination method is discussed with great emphasis.Experiments are done successfully with perfect results verifying all the formulas and the methods above.
文摘Based on the characteristics of ATM system and the special requirement of financial transaction, an overall design of hardware and software structure of ATM was made. For software structure, the pattern of modules and table? drive is adopted to realize the security of financial transaction and the diagnosis of communication fault. A new method, which is based on the application layer, transport layer and network layer, is used for diagnosing communication fault. Supporting both magnetic card and IC card, the system has been put into use in real financial systems, and has brought about both economic and social effects.
文摘A hardware/software field programmable gate array （FPGA）-based driver system was proposed and demonstrated for the KAF-39000 large area high resolution charge coupled device （CCD）. The requirements of the KAF-39000 driver system were analyzed. The structure of ＂microprocessor with application specific integrated circuit （ASIC） chips＂ was implemented to design the driver system. The system test results showed that dual channels of imaging analog data were obtained with a frame rate of 0.87frame/s. The frequencies of horizontal timing and vertical timing were 22.9MHz and 28.7kHz, respectively, which almost reached the theoretical value of 24 MHz and 30kHz, respectively.
