在 SOI(Silicon on Insulator)结构硅膜上面生长一层 Si Ge合金 ,采用类似 SOICMOS工艺制作成具有Si Ge沟道的 SOICMOS集成电路。该电路不仅具有 SOICMOS电路的优点 ,而且因为 Si Ge中的载流子迁移率明显高于 Si中载流子的迁移率 ,所以...在 SOI(Silicon on Insulator)结构硅膜上面生长一层 Si Ge合金 ,采用类似 SOICMOS工艺制作成具有Si Ge沟道的 SOICMOS集成电路。该电路不仅具有 SOICMOS电路的优点 ,而且因为 Si Ge中的载流子迁移率明显高于 Si中载流子的迁移率 ,所以提高了电路的速度和驱动能力。另外由于两种极性的 SOI MOSFET都采用 Si Ge沟道 ,就避免了只有 SOIPMOSFET采用 Si Ge沟道带来的选择性生长 Si Ge层的麻烦。采用二维工艺模拟得到了器件的结构 ,并以此结构参数进行了器件模拟。模拟结果表明 ,N沟和 P沟两种 MOSFET的驱动电流都有所增加 。展开更多
为研究深亚微米尺度下应变 Si Ge沟改进 PMOSFET器件性能的有效性 ,运用二维数值模拟程序MEDICI模拟和分析了 0 .1 8μm有效沟长 Si Ge PMOS及 Si PMOS器件特性。Si Ge PMOS垂直方向采用 Si/Si Ge/Si结构 ,横向结构同常规 PMOS,N+ -pol...为研究深亚微米尺度下应变 Si Ge沟改进 PMOSFET器件性能的有效性 ,运用二维数值模拟程序MEDICI模拟和分析了 0 .1 8μm有效沟长 Si Ge PMOS及 Si PMOS器件特性。Si Ge PMOS垂直方向采用 Si/Si Ge/Si结构 ,横向结构同常规 PMOS,N+ -poly栅结合 P型δ掺杂层获得了合理阈值电压及空穴局域化。研究表明 ,经适当设计的 Si Ge PMOS比对应 Si PMOS的 IDmax、gm、f T均提高 1 0 0 %以上 ,表明深亚微米尺度 Si展开更多
A new 125mm UHV/CVD SiGe/Si epitaxy equipment SGE500 capable of commercialization is constructed and device-level SiGe HBT material is grown.A polysilicon emitter (PolyE) double mesa microwave power SiGe HBT showing e...A new 125mm UHV/CVD SiGe/Si epitaxy equipment SGE500 capable of commercialization is constructed and device-level SiGe HBT material is grown.A polysilicon emitter (PolyE) double mesa microwave power SiGe HBT showing excellent low current DC characteristics with β=60@V CE/I C=9.0V/300μA,β=100@5V/50mA,BV CBO=22V,f t/f max=5.4GHz/7.7GHz@3V/10mA is demonstrated.The PolyE SiGe HBT needs only 6 lithographical steps and cancels the growth of the thick emitter epitaxy layer,both of which show great potential for volume production.A 60-finger class-A SiGe linear power amplifer (PA) w ith 22dBm of 1dB compress point output power (P 1dB),11dB of power gain (G p) and 26.1% of power added efficiency (PAE) @900MHz,3.5V/0.2A is demonstrated.Another 120-finger class-A SiGe PA with 33.3dBm (2.1W) of P out,10.3dB of G p and 33.9% of PAE @900MHz,11V/0.52A is also demonstrated.展开更多
Strained-Si pMOSFETs on very thin relaxed virtua l SiGe substrates are presented.The 240nm relaxed virtual Si 0.8 Ge 0.2 layer on 100nm low-temperature Si(LT-Si) is grown on Si(100) substrates by molecular be...Strained-Si pMOSFETs on very thin relaxed virtua l SiGe substrates are presented.The 240nm relaxed virtual Si 0.8 Ge 0.2 layer on 100nm low-temperature Si(LT-Si) is grown on Si(100) substrates by molecular beam epitaxy.LT-Si buffer layer is used to release stress of the SiGe layer so as to make it relaxed.DCXRD,AFM,and TEM measurements indicate that the strain relaxed degree of SiGe layer is 85%,RMS roughness is 1.02nm,and threading dislocation density is at most 107cm -2 .At room temperature,a maximum hole mobility of strained-Si pMOSFET is 140cm2/(V·s).Device performance is comparable to that of devices achieved on several microns thick relaxed virtual SiGe substrates.展开更多
Good performance SiGe power amplifiers applicable to wireless communications are demonstrated.The output power can reach more than 30dBm in class B mode.And in class AB mode,the output power at 1dB compression point (...Good performance SiGe power amplifiers applicable to wireless communications are demonstrated.The output power can reach more than 30dBm in class B mode.And in class AB mode,the output power at 1dB compression point ( P 1dB ) is 24dBm,the output third order intercept (TOI) power is 39dBm under V cc of 4V.The highest power added efficiency (PAE) and PAE at 1dB compression point are 34% and 25%,respectively.The adjacent channel power rejection for CDMA signal is more than 42dBc,which complies with IS95 specification.展开更多
Based on an analysis of symmetry, the dispersion relations near the Ai valley in strained Si1-x Gex （0≤x〈0.45）/ （001）, （111）, （101）Si are derived using the KP method with perturbation theory. These relations...Based on an analysis of symmetry, the dispersion relations near the Ai valley in strained Si1-x Gex （0≤x〈0.45）/ （001）, （111）, （101）Si are derived using the KP method with perturbation theory. These relations demonstrate that △^i levels in strained Si1-x Gex are different from the △1 level in relaxed Si1-x Gex, while the longitudinal and transverse masses （m1^＊ and mt^＊ ） are unchanged under strain. The energy shift between the △^i levels and the △1 level follows the linear deformation potential theory. Finally,a description of the conduction band （CB） edge in biaxially strained layers is given.展开更多
A novel MBE-grown method using low-temperature (L T) Si technology is introduced into the fabrication of strained Si channel heter ojunction pMOSFETs.By sandwiching a low-temperature Si layer between Si buffer and S...A novel MBE-grown method using low-temperature (L T) Si technology is introduced into the fabrication of strained Si channel heter ojunction pMOSFETs.By sandwiching a low-temperature Si layer between Si buffer and SiGe layer,the strain relaxation degree of the SiGe layer is increased.At th e same time,the threading dislocations (TDs) are hold back from propagating to t he surface.As a result,the thickness of relaxed Si 1-xGe x epitax y layer on bulk silicon is reduced from several micrometers using UHVCVD to less than 400nm(x=0.2),which will improve the heat dissipation of devices.AFM t ests of strained Si surface show RMS is less than 1.02nm.The DC characters meas ured by HP 4155B indicate that hole mobility μ p has 25% of maximum enhanc ement compared to that of bulk Si pMOSFET processed similarly.展开更多
An optimized condition for defect passivation by the hot-wire technique was established. Effects of hydrogenation for polycrystalline SiGe （poly-Si1-xGex ） thin films were estimated by investigating the dark conduct...An optimized condition for defect passivation by the hot-wire technique was established. Effects of hydrogenation for polycrystalline SiGe （poly-Si1-xGex ） thin films were estimated by investigating the dark conductivity and activation energy that derive from the conductivity as a function of the temperature. The results show that this technique can effectively reduce defects present in poly-Si1-xGex films. By optimizing the substrate and filament temperatures,the treatment can be accomplished in a short time of 20-30min, which is considerably shorter than other hydrogenation techniques.展开更多
The influence of thermal treatment on Si 1-x Ge x/Si multiple-quantum wells (MQW) p-i-n photodiodes has been investigated by photocurrent spectroscopy combined with X-ray double crystal dif...The influence of thermal treatment on Si 1-x Ge x/Si multiple-quantum wells (MQW) p-i-n photodiodes has been investigated by photocurrent spectroscopy combined with X-ray double crystal diffraction.The cutoff wavelength is significantly reduced due to the Si-Ge interdiffusion and partial relaxation of the strained SiGe alloy.The values of the blue shift increase slowly with the annealing temperatures in the range of 750℃ to 850℃.However,the nonlinear changes in photocurrent intensities of the samples annealed at different temperatures have been observed,which is mainly dominated by the generation of misfit dislocations and the reduction of the point defects in the heating process.展开更多
The structure and microwave characteristics of low-voltage SiGe power HBTs are given.With this structure,the device can operate in a low-voltage and high-current state.By using an interdigital emitter strip layout and...The structure and microwave characteristics of low-voltage SiGe power HBTs are given.With this structure,the device can operate in a low-voltage and high-current state.By using an interdigital emitter strip layout and the operating voltage ranging from 3 to 4V,the output power in Class C operation can reach 1 65W at 1GHz,with the gain of 8dB.The highest collector efficiency is 67 8% under 3V.展开更多
The strained SiGe material has been grown by using the newly developed High Vacuum/Rapid Thermal Processing/Chemical Vapor Deposition (HV/RTP/CVD) system.Device quality material is grown by handling process after car...The strained SiGe material has been grown by using the newly developed High Vacuum/Rapid Thermal Processing/Chemical Vapor Deposition (HV/RTP/CVD) system.Device quality material is grown by handling process after careful design. The Ge fraction varies up to 0 25, and the n and p type doping is well controlled,which are both adapted to the fabrication of Heterojunction Bipolar Transistors (HBT). The SiGe HBT structure, namely n Si/i p + i SiGe/n Si structure, has been investigated, with which, the HBTs are fabricated and show good performance. The new system has been proved potential and practicable.展开更多
GeSi source/drain structure is purposefully adopted in SOI p MOSFET's to suppress the short channel effect (SCE).The impact of GeSi material (as source only,drain only or both source and drain) on the threshold v...GeSi source/drain structure is purposefully adopted in SOI p MOSFET's to suppress the short channel effect (SCE).The impact of GeSi material (as source only,drain only or both source and drain) on the threshold voltage rolling off and DIBL effect is thoroughly investigated,as well as the influence of the Ge concentration and silicon film thickness.The Ge concentration should be carefully chosen as a tradeoff between the driving current and SCE improvement.The detailed physics is explained.展开更多
H2Ge=Si： and its derivatives （X2Ge=Si：, X=H, Me, F, C1, Br, Ph, Ar, ...） are new species. Its cycloaddition reactions are new area for the study of silylene chemistry. The cycloaddition reaction mechanism of singl...H2Ge=Si： and its derivatives （X2Ge=Si：, X=H, Me, F, C1, Br, Ph, Ar, ...） are new species. Its cycloaddition reactions are new area for the study of silylene chemistry. The cycloaddition reaction mechanism of singlet H2Ge=Si： and formaldehyde has been investigated with the MP2/aug-cc-pVDZ method. From the potential energy profile, it could be predicted that the reaction has one dominant reaction pathway. The reaction rule is that two reactants firstly form a four-membered Ge-heterocyclic ring silylene through the [2＋2] cycloaddition reaction. Because of the 3p unoccupied orbital of Si： atom in the four-membered Ge-heterocyclic ring silylene and the π orbital of formaldehyde forming a π--p donor-acceptor bond, the four-membered Ge-heterocyclic ring silylene further combines with formaldehyde to form an intermediate. Because the Si： atom in the intermediate undergoes sp3 hybridization after transition state, then the intermediate isomerizes to a spiro-Si-heterocyclic ring compound involving Ge via a transition state. The result indicates the laws of cycloaddition reaction between H2Ge=Si： or its derivatives （X2Ge=Si：, X=H, Me, F, Cl, Br, Ph, Ar, ...） and asymmetric π-bonded compounds are significant for the synthesis of small-ring involving Si and Ge and spiro-Si-heterocyclic ring compounds involving Ge.展开更多
The process parameters are adjusted and the process procedure is simplified on the basis of precursor's work and the strained Si channel SiGe n MOSFET is fabricated successfully.This n MOSFET takes the strained...The process parameters are adjusted and the process procedure is simplified on the basis of precursor's work and the strained Si channel SiGe n MOSFET is fabricated successfully.This n MOSFET takes the strained Si layer(which is deposited on the relaxed SiGe buffer layer) as current channel and can provide a 48 5% improvement in electron mobility while keeping the gate voltage as 1V.展开更多
Through the theoretical analysis and computer simulation,the optimized design principles for Si/SiGe PMOSFETs are given,including the choice of gate materials,the determination of Ge percentage and the profile in SiGe...Through the theoretical analysis and computer simulation,the optimized design principles for Si/SiGe PMOSFETs are given,including the choice of gate materials,the determination of Ge percentage and the profile in SiGe channel,the thickness optimization of dioxide and silicon cap layer,and the adjustment of threshold voltage.In light of them,a SiGe PMOSFET is designed and fabricated successfully.The measurements indicate that the transconductance is 45mS/mm (300K) and 92mS/mm (77K) for SiGe PMOSFET's (L=2μm),while it is 33mS/mm (300K) and 39mS/mm (77K) for Si PMOSFET.展开更多
This paper discusses the design of a 10 Gb/s laser diode driver implemented in SiGe BiCMOS technology. The laser diode driver is composed of an input buffer, a predriver circuit and an output current switch stage. Wit...This paper discusses the design of a 10 Gb/s laser diode driver implemented in SiGe BiCMOS technology. The laser diode driver is composed of an input buffer, a predriver circuit and an output current switch stage. With the current mode logic （CML） structure, the input buffer and the predriver circuit have the capability of transmission and amplification of high speed data. By employing MOS-HBT cascode structure as the output stage, the laser diode driver exhibits very high speed and efficiency working at the 10 Gb/s data rate. The core circuit is operated under a 3. 3 V supply, while the output stage is operated under 5.5 V for sufficient headroom across the laser diode. The chip occupies a die area of 600 μm × 800μm. Measurements on chip show clear electrical eye diagrams over 10 Gb/s, which can well meet the specifications defined by SDH STM64/SONET OC192 and a 10 Gb/s Ethemet eye mask. Under a 5. 5 V supply voltage, the maximum output swing is 3.0 V with a 50 12 load （the corresponding modulation current is 60 mA）, and the total power dissipation is 660 mW.展开更多
A high performance 70nm CMOS device has been demonstrated for the first time in the continent, China. Some innovations in techniques are applied to restrain the short channel effect and improve the driving ability, ...A high performance 70nm CMOS device has been demonstrated for the first time in the continent, China. Some innovations in techniques are applied to restrain the short channel effect and improve the driving ability, such as 3nm nitrided oxide, dual poly Si gate electrode, novel super steep retrograde channel doping by heavy ion implantation, ultra shallow S/D extension formed by Ge PAI(Pre Amorphism Implantation) plus LEI(Low Energy Implantation), thin and low resistance Ti SALICIDE by Ge PAI and special cleaning, etc. The shortest channel length of the CMOS device is 70nm. The threshold voltages, G m and off current are 0 28V,490mS·mm -1 and 0 08nA/μm for NMOS and -0 3V,340mS·mm -1 and 0 2nA/μm for PMOS, respectively. Delays of 23 5ps/stage at 1 5V, 17 5ps/stage at 2 0V and 12 5ps/stage at 3V are achieved in the 57 stage unloaded 100nm CMOS ring oscillator circuits.展开更多
Based on theoretical analysis and computer-aided simulation, optimized design principles for Si/SiGe PMOSFET are given in this paper, which include choice of gate materials,determination of germanium percentage and pr...Based on theoretical analysis and computer-aided simulation, optimized design principles for Si/SiGe PMOSFET are given in this paper, which include choice of gate materials,determination of germanium percentage and profile in SiGe channel, optimization of thickness of dioxide and silicon cap layer, and adjustment of threshold voltage. In the light of these principles,a SiGe PMOSFET is designed and fabricated successfully. Measurement indicates that the SiGe PMOSFET's (L=2μm) transconductance is 45 mS/mm (300K) and 92mS/mm (77K), while that is 33 mS/mm (300K) and 39mS/mm (77K) in Si PMOSFET with the same structure.展开更多
Using double crystal X-rays diffraction (DCXRD) and atomic force microscopy (AFM), the results of Ge x Si 1- x grown by UHV/CVD from Si 2H 6 and SiH 4 are analyzed and compared. Adsorbates can migrate to the energy-fa...Using double crystal X-rays diffraction (DCXRD) and atomic force microscopy (AFM), the results of Ge x Si 1- x grown by UHV/CVD from Si 2H 6 and SiH 4 are analyzed and compared. Adsorbates can migrate to the energy-favoring position due to the slow growth rate from SiH 4. In this case, a Si buffer that isolates the effect of substrate on epilayer could not be grown, which results in a pit penetrating into epilayer and buffer. The FWHM is 0.055° in DCXRD from SiH 4. The presence of diffraction fringes is an indication of an excellent crystalline quality. The roughness of the surface is improved if grown by Si 2H 6; however, the crystal quality of the Ge x Si 1- x material became worse than that from SiH 4 due to much larger growth rate from Si 2H 6. The content of Ge is obtained from DCXRD, which indicates the growth rate from Si 2H 6 is largest, then GeH 4, and that from SiH 4 is least.展开更多
In this paper we present a study on the influence of the number and the thickness of silicon spacer layer on the optical properties of single-and multi-layers of self assembled Ge/Si(001) islands performed by means of...In this paper we present a study on the influence of the number and the thickness of silicon spacer layer on the optical properties of single-and multi-layers of self assembled Ge/Si(001) islands performed by means of cathodoluminescence spectroscopy,high resolution X-ray diffraction and transmission electron microscopy. In single-layer sample,we do not evidence dependence of the island no-phonon emission peak position on the silicon cap-layer thickness. In multi-layer samples having a thin(33 nm) silicon spacer layer the no-phonon emission energy value progressively blue-shifts for an increasing number of island layers. This is interpreted as an enhanced intermixing driven by the strain interaction existing between island layers. On the contrary,island emission energy position is independent on the number of layers in the sample series having a thicker spacer layer(60 nm) . These findings are consistent with the X-ray diffraction observation that islands belonging to different layers have the same composition. As a consequence we can conclude that multilayers with 60-nm spaced islands layer are more homogeneous and ordered.展开更多
文摘在 SOI(Silicon on Insulator)结构硅膜上面生长一层 Si Ge合金 ,采用类似 SOICMOS工艺制作成具有Si Ge沟道的 SOICMOS集成电路。该电路不仅具有 SOICMOS电路的优点 ,而且因为 Si Ge中的载流子迁移率明显高于 Si中载流子的迁移率 ,所以提高了电路的速度和驱动能力。另外由于两种极性的 SOI MOSFET都采用 Si Ge沟道 ,就避免了只有 SOIPMOSFET采用 Si Ge沟道带来的选择性生长 Si Ge层的麻烦。采用二维工艺模拟得到了器件的结构 ,并以此结构参数进行了器件模拟。模拟结果表明 ,N沟和 P沟两种 MOSFET的驱动电流都有所增加 。
文摘为研究深亚微米尺度下应变 Si Ge沟改进 PMOSFET器件性能的有效性 ,运用二维数值模拟程序MEDICI模拟和分析了 0 .1 8μm有效沟长 Si Ge PMOS及 Si PMOS器件特性。Si Ge PMOS垂直方向采用 Si/Si Ge/Si结构 ,横向结构同常规 PMOS,N+ -poly栅结合 P型δ掺杂层获得了合理阈值电压及空穴局域化。研究表明 ,经适当设计的 Si Ge PMOS比对应 Si PMOS的 IDmax、gm、f T均提高 1 0 0 %以上 ,表明深亚微米尺度 Si
文摘A new 125mm UHV/CVD SiGe/Si epitaxy equipment SGE500 capable of commercialization is constructed and device-level SiGe HBT material is grown.A polysilicon emitter (PolyE) double mesa microwave power SiGe HBT showing excellent low current DC characteristics with β=60@V CE/I C=9.0V/300μA,β=100@5V/50mA,BV CBO=22V,f t/f max=5.4GHz/7.7GHz@3V/10mA is demonstrated.The PolyE SiGe HBT needs only 6 lithographical steps and cancels the growth of the thick emitter epitaxy layer,both of which show great potential for volume production.A 60-finger class-A SiGe linear power amplifer (PA) w ith 22dBm of 1dB compress point output power (P 1dB),11dB of power gain (G p) and 26.1% of power added efficiency (PAE) @900MHz,3.5V/0.2A is demonstrated.Another 120-finger class-A SiGe PA with 33.3dBm (2.1W) of P out,10.3dB of G p and 33.9% of PAE @900MHz,11V/0.52A is also demonstrated.
文摘Strained-Si pMOSFETs on very thin relaxed virtua l SiGe substrates are presented.The 240nm relaxed virtual Si 0.8 Ge 0.2 layer on 100nm low-temperature Si(LT-Si) is grown on Si(100) substrates by molecular beam epitaxy.LT-Si buffer layer is used to release stress of the SiGe layer so as to make it relaxed.DCXRD,AFM,and TEM measurements indicate that the strain relaxed degree of SiGe layer is 85%,RMS roughness is 1.02nm,and threading dislocation density is at most 107cm -2 .At room temperature,a maximum hole mobility of strained-Si pMOSFET is 140cm2/(V·s).Device performance is comparable to that of devices achieved on several microns thick relaxed virtual SiGe substrates.
文摘Good performance SiGe power amplifiers applicable to wireless communications are demonstrated.The output power can reach more than 30dBm in class B mode.And in class AB mode,the output power at 1dB compression point ( P 1dB ) is 24dBm,the output third order intercept (TOI) power is 39dBm under V cc of 4V.The highest power added efficiency (PAE) and PAE at 1dB compression point are 34% and 25%,respectively.The adjacent channel power rejection for CDMA signal is more than 42dBc,which complies with IS95 specification.
文摘Based on an analysis of symmetry, the dispersion relations near the Ai valley in strained Si1-x Gex （0≤x〈0.45）/ （001）, （111）, （101）Si are derived using the KP method with perturbation theory. These relations demonstrate that △^i levels in strained Si1-x Gex are different from the △1 level in relaxed Si1-x Gex, while the longitudinal and transverse masses （m1^＊ and mt^＊ ） are unchanged under strain. The energy shift between the △^i levels and the △1 level follows the linear deformation potential theory. Finally,a description of the conduction band （CB） edge in biaxially strained layers is given.
文摘A novel MBE-grown method using low-temperature (L T) Si technology is introduced into the fabrication of strained Si channel heter ojunction pMOSFETs.By sandwiching a low-temperature Si layer between Si buffer and SiGe layer,the strain relaxation degree of the SiGe layer is increased.At th e same time,the threading dislocations (TDs) are hold back from propagating to t he surface.As a result,the thickness of relaxed Si 1-xGe x epitax y layer on bulk silicon is reduced from several micrometers using UHVCVD to less than 400nm(x=0.2),which will improve the heat dissipation of devices.AFM t ests of strained Si surface show RMS is less than 1.02nm.The DC characters meas ured by HP 4155B indicate that hole mobility μ p has 25% of maximum enhanc ement compared to that of bulk Si pMOSFET processed similarly.
文摘An optimized condition for defect passivation by the hot-wire technique was established. Effects of hydrogenation for polycrystalline SiGe （poly-Si1-xGex ） thin films were estimated by investigating the dark conductivity and activation energy that derive from the conductivity as a function of the temperature. The results show that this technique can effectively reduce defects present in poly-Si1-xGex films. By optimizing the substrate and filament temperatures,the treatment can be accomplished in a short time of 20-30min, which is considerably shorter than other hydrogenation techniques.
文摘The influence of thermal treatment on Si 1-x Ge x/Si multiple-quantum wells (MQW) p-i-n photodiodes has been investigated by photocurrent spectroscopy combined with X-ray double crystal diffraction.The cutoff wavelength is significantly reduced due to the Si-Ge interdiffusion and partial relaxation of the strained SiGe alloy.The values of the blue shift increase slowly with the annealing temperatures in the range of 750℃ to 850℃.However,the nonlinear changes in photocurrent intensities of the samples annealed at different temperatures have been observed,which is mainly dominated by the generation of misfit dislocations and the reduction of the point defects in the heating process.
文摘The structure and microwave characteristics of low-voltage SiGe power HBTs are given.With this structure,the device can operate in a low-voltage and high-current state.By using an interdigital emitter strip layout and the operating voltage ranging from 3 to 4V,the output power in Class C operation can reach 1 65W at 1GHz,with the gain of 8dB.The highest collector efficiency is 67 8% under 3V.
文摘The strained SiGe material has been grown by using the newly developed High Vacuum/Rapid Thermal Processing/Chemical Vapor Deposition (HV/RTP/CVD) system.Device quality material is grown by handling process after careful design. The Ge fraction varies up to 0 25, and the n and p type doping is well controlled,which are both adapted to the fabrication of Heterojunction Bipolar Transistors (HBT). The SiGe HBT structure, namely n Si/i p + i SiGe/n Si structure, has been investigated, with which, the HBTs are fabricated and show good performance. The new system has been proved potential and practicable.
文摘GeSi source/drain structure is purposefully adopted in SOI p MOSFET's to suppress the short channel effect (SCE).The impact of GeSi material (as source only,drain only or both source and drain) on the threshold voltage rolling off and DIBL effect is thoroughly investigated,as well as the influence of the Ge concentration and silicon film thickness.The Ge concentration should be carefully chosen as a tradeoff between the driving current and SCE improvement.The detailed physics is explained.
文摘H2Ge=Si： and its derivatives （X2Ge=Si：, X=H, Me, F, C1, Br, Ph, Ar, ...） are new species. Its cycloaddition reactions are new area for the study of silylene chemistry. The cycloaddition reaction mechanism of singlet H2Ge=Si： and formaldehyde has been investigated with the MP2/aug-cc-pVDZ method. From the potential energy profile, it could be predicted that the reaction has one dominant reaction pathway. The reaction rule is that two reactants firstly form a four-membered Ge-heterocyclic ring silylene through the [2＋2] cycloaddition reaction. Because of the 3p unoccupied orbital of Si： atom in the four-membered Ge-heterocyclic ring silylene and the π orbital of formaldehyde forming a π--p donor-acceptor bond, the four-membered Ge-heterocyclic ring silylene further combines with formaldehyde to form an intermediate. Because the Si： atom in the intermediate undergoes sp3 hybridization after transition state, then the intermediate isomerizes to a spiro-Si-heterocyclic ring compound involving Ge via a transition state. The result indicates the laws of cycloaddition reaction between H2Ge=Si： or its derivatives （X2Ge=Si：, X=H, Me, F, Cl, Br, Ph, Ar, ...） and asymmetric π-bonded compounds are significant for the synthesis of small-ring involving Si and Ge and spiro-Si-heterocyclic ring compounds involving Ge.
文摘The process parameters are adjusted and the process procedure is simplified on the basis of precursor's work and the strained Si channel SiGe n MOSFET is fabricated successfully.This n MOSFET takes the strained Si layer(which is deposited on the relaxed SiGe buffer layer) as current channel and can provide a 48 5% improvement in electron mobility while keeping the gate voltage as 1V.
文摘Through the theoretical analysis and computer simulation,the optimized design principles for Si/SiGe PMOSFETs are given,including the choice of gate materials,the determination of Ge percentage and the profile in SiGe channel,the thickness optimization of dioxide and silicon cap layer,and the adjustment of threshold voltage.In light of them,a SiGe PMOSFET is designed and fabricated successfully.The measurements indicate that the transconductance is 45mS/mm (300K) and 92mS/mm (77K) for SiGe PMOSFET's (L=2μm),while it is 33mS/mm (300K) and 39mS/mm (77K) for Si PMOSFET.
基金The National High Technology Research and Development Program of China(863 Program)(No.2006AA01Z284)
文摘This paper discusses the design of a 10 Gb/s laser diode driver implemented in SiGe BiCMOS technology. The laser diode driver is composed of an input buffer, a predriver circuit and an output current switch stage. With the current mode logic （CML） structure, the input buffer and the predriver circuit have the capability of transmission and amplification of high speed data. By employing MOS-HBT cascode structure as the output stage, the laser diode driver exhibits very high speed and efficiency working at the 10 Gb/s data rate. The core circuit is operated under a 3. 3 V supply, while the output stage is operated under 5.5 V for sufficient headroom across the laser diode. The chip occupies a die area of 600 μm × 800μm. Measurements on chip show clear electrical eye diagrams over 10 Gb/s, which can well meet the specifications defined by SDH STM64/SONET OC192 and a 10 Gb/s Ethemet eye mask. Under a 5. 5 V supply voltage, the maximum output swing is 3.0 V with a 50 12 load （the corresponding modulation current is 60 mA）, and the total power dissipation is 660 mW.
文摘A high performance 70nm CMOS device has been demonstrated for the first time in the continent, China. Some innovations in techniques are applied to restrain the short channel effect and improve the driving ability, such as 3nm nitrided oxide, dual poly Si gate electrode, novel super steep retrograde channel doping by heavy ion implantation, ultra shallow S/D extension formed by Ge PAI(Pre Amorphism Implantation) plus LEI(Low Energy Implantation), thin and low resistance Ti SALICIDE by Ge PAI and special cleaning, etc. The shortest channel length of the CMOS device is 70nm. The threshold voltages, G m and off current are 0 28V,490mS·mm -1 and 0 08nA/μm for NMOS and -0 3V,340mS·mm -1 and 0 2nA/μm for PMOS, respectively. Delays of 23 5ps/stage at 1 5V, 17 5ps/stage at 2 0V and 12 5ps/stage at 3V are achieved in the 57 stage unloaded 100nm CMOS ring oscillator circuits.
基金Supported by National Key Laboratory Fund (99Js09 5.1)
文摘Based on theoretical analysis and computer-aided simulation, optimized design principles for Si/SiGe PMOSFET are given in this paper, which include choice of gate materials,determination of germanium percentage and profile in SiGe channel, optimization of thickness of dioxide and silicon cap layer, and adjustment of threshold voltage. In the light of these principles,a SiGe PMOSFET is designed and fabricated successfully. Measurement indicates that the SiGe PMOSFET's (L=2μm) transconductance is 45 mS/mm (300K) and 92mS/mm (77K), while that is 33 mS/mm (300K) and 39mS/mm (77K) in Si PMOSFET with the same structure.
基金The National Natural Science Foundation of China
文摘Using double crystal X-rays diffraction (DCXRD) and atomic force microscopy (AFM), the results of Ge x Si 1- x grown by UHV/CVD from Si 2H 6 and SiH 4 are analyzed and compared. Adsorbates can migrate to the energy-favoring position due to the slow growth rate from SiH 4. In this case, a Si buffer that isolates the effect of substrate on epilayer could not be grown, which results in a pit penetrating into epilayer and buffer. The FWHM is 0.055° in DCXRD from SiH 4. The presence of diffraction fringes is an indication of an excellent crystalline quality. The roughness of the surface is improved if grown by Si 2H 6; however, the crystal quality of the Ge x Si 1- x material became worse than that from SiH 4 due to much larger growth rate from Si 2H 6. The content of Ge is obtained from DCXRD, which indicates the growth rate from Si 2H 6 is largest, then GeH 4, and that from SiH 4 is least.
文摘In this paper we present a study on the influence of the number and the thickness of silicon spacer layer on the optical properties of single-and multi-layers of self assembled Ge/Si(001) islands performed by means of cathodoluminescence spectroscopy,high resolution X-ray diffraction and transmission electron microscopy. In single-layer sample,we do not evidence dependence of the island no-phonon emission peak position on the silicon cap-layer thickness. In multi-layer samples having a thin(33 nm) silicon spacer layer the no-phonon emission energy value progressively blue-shifts for an increasing number of island layers. This is interpreted as an enhanced intermixing driven by the strain interaction existing between island layers. On the contrary,island emission energy position is independent on the number of layers in the sample series having a thicker spacer layer(60 nm) . These findings are consistent with the X-ray diffraction observation that islands belonging to different layers have the same composition. As a consequence we can conclude that multilayers with 60-nm spaced islands layer are more homogeneous and ordered.
