An 1∶8 frequency divider is designed and realized in a 0 35μm standard CMOS technology.The chip consists of three stages of 1∶2 divider cells,which are constructed with source couple logic (SCL) flip flops.By rev...An 1∶8 frequency divider is designed and realized in a 0 35μm standard CMOS technology.The chip consists of three stages of 1∶2 divider cells,which are constructed with source couple logic (SCL) flip flops.By revising the traditional topology of SCL flip flop,a divider with better performances is got.The results of measurement show that the whole chip achieves the frequency division at more than 8 5GHz.Each 1∶2 divider consumes about 11mW from a 3 3V supply.The divider can be used in RF and optic fiber transceivers and other high speed systems.展开更多
A 1∶4 static frequency divider has been designed and realized in a 0.35-micron standard CMOS technology. The chip consists of two identical 1∶2 divider cells, which are based on SCL (Source Coupled Logic) flip-flops...A 1∶4 static frequency divider has been designed and realized in a 0.35-micron standard CMOS technology. The chip consists of two identical 1∶2 divider cells, which are based on SCL (Source Coupled Logic) flip-flops. By revising the traditional topology of SCL flip-flop, we get a divider with better performances. Measurement results show that the whole chip achieves the frequency division at more than 6GHz. Each 1∶2 divider consumes 11mW from a 3.3V supply. The divider can be used in RF and Optic-fiber Transceivers and other high-speed systems.展开更多
文摘An 1∶8 frequency divider is designed and realized in a 0 35μm standard CMOS technology.The chip consists of three stages of 1∶2 divider cells,which are constructed with source couple logic (SCL) flip flops.By revising the traditional topology of SCL flip flop,a divider with better performances is got.The results of measurement show that the whole chip achieves the frequency division at more than 8 5GHz.Each 1∶2 divider consumes about 11mW from a 3 3V supply.The divider can be used in RF and optic fiber transceivers and other high speed systems.
文摘A 1∶4 static frequency divider has been designed and realized in a 0.35-micron standard CMOS technology. The chip consists of two identical 1∶2 divider cells, which are based on SCL (Source Coupled Logic) flip-flops. By revising the traditional topology of SCL flip-flop, we get a divider with better performances. Measurement results show that the whole chip achieves the frequency division at more than 6GHz. Each 1∶2 divider consumes 11mW from a 3.3V supply. The divider can be used in RF and Optic-fiber Transceivers and other high-speed systems.
