采用标准CMOS工艺设计出PDP(Plasma Display Panel)选址芯片,重点设计出一种高压结构—HV-CMOS(High Voltage CMOS)结构,采用单阱非外延工艺以降低生产难度和成本,实现了高低压之间的兼容。同时采用TSUPREM-4对该结构进行工艺模拟、并用...采用标准CMOS工艺设计出PDP(Plasma Display Panel)选址芯片,重点设计出一种高压结构—HV-CMOS(High Voltage CMOS)结构,采用单阱非外延工艺以降低生产难度和成本,实现了高低压之间的兼容。同时采用TSUPREM-4对该结构进行工艺模拟、并用MEDICI分析其电流—电压和击穿等特性,说明该结构可以满足设计要求。展开更多
A novel dual gate oxide （DGO） process is proposed to improve the performance of high voltage CMOS （HVCMOS） devices and the compatibility between thick gate oxide devices and thin gate oxide devices. An extra sidew...A novel dual gate oxide （DGO） process is proposed to improve the performance of high voltage CMOS （HVCMOS） devices and the compatibility between thick gate oxide devices and thin gate oxide devices. An extra sidewall is added in this DGO process to round off the step formed after etching the thick gate oxide and poly-silicon. The breakdown voltages of high voltage nMOS （HVnMOS） and high voltage pMOS （HVpMOS） are 168 and - 158V, respectively. Excellent performances are realized for both HVnMOS and HVpMOS devices. Experimental results demonstrate that the HVCMOS devices work safely at an operation voltage of 100V.展开更多
This study deals with a new evaluation method of nuclear electromagnetic pulse （NEMP） vulnerability on cots electronic equipments. The method consists in comparing electromagnetic compatibility （EMC） test severiti...This study deals with a new evaluation method of nuclear electromagnetic pulse （NEMP） vulnerability on cots electronic equipments. The method consists in comparing electromagnetic compatibility （EMC） test severities to NEMP conducted stresses. The comparison uses five characteristic criteria of the induced stresses, calculated with an analytic method. The process is based on a software named ＂SUSIE＂ （in French： SUSceptibilite a I＇IEMN ＂Impulsion ElectroMagnttique d＇origine Nucl6aire Haute Altitude＂）. Today, only conducted stresses are analyzed. An evolution is planned in 2013 to determine the equivalent vulnerability of radiated stresses and to validate the software.展开更多
文摘采用标准CMOS工艺设计出PDP(Plasma Display Panel)选址芯片,重点设计出一种高压结构—HV-CMOS(High Voltage CMOS)结构,采用单阱非外延工艺以降低生产难度和成本,实现了高低压之间的兼容。同时采用TSUPREM-4对该结构进行工艺模拟、并用MEDICI分析其电流—电压和击穿等特性,说明该结构可以满足设计要求。
文摘A novel dual gate oxide （DGO） process is proposed to improve the performance of high voltage CMOS （HVCMOS） devices and the compatibility between thick gate oxide devices and thin gate oxide devices. An extra sidewall is added in this DGO process to round off the step formed after etching the thick gate oxide and poly-silicon. The breakdown voltages of high voltage nMOS （HVnMOS） and high voltage pMOS （HVpMOS） are 168 and - 158V, respectively. Excellent performances are realized for both HVnMOS and HVpMOS devices. Experimental results demonstrate that the HVCMOS devices work safely at an operation voltage of 100V.
文摘This study deals with a new evaluation method of nuclear electromagnetic pulse （NEMP） vulnerability on cots electronic equipments. The method consists in comparing electromagnetic compatibility （EMC） test severities to NEMP conducted stresses. The comparison uses five characteristic criteria of the induced stresses, calculated with an analytic method. The process is based on a software named ＂SUSIE＂ （in French： SUSceptibilite a I＇IEMN ＂Impulsion ElectroMagnttique d＇origine Nucl6aire Haute Altitude＂）. Today, only conducted stresses are analyzed. An evolution is planned in 2013 to determine the equivalent vulnerability of radiated stresses and to validate the software.
