In recent years, more attention has been paid on artificial life researches. Artificial life（AL） is a research on regulating gene parameters of digital organisms under complicated problematic environments through na...In recent years, more attention has been paid on artificial life researches. Artificial life（AL） is a research on regulating gene parameters of digital organisms under complicated problematic environments through natural selections and evolutions to achieve the final emergence of intelligence. Most recent studies focused on solving certain real problems by artificial life methods, yet without much address on the AL life basic mechanism. The real problems are often very complicated, and the proposed methods sometimes seem too simple to handle those problems. This study proposed a new approach in AL research, named ＂generalized artificial life structure（GALS）＂, in which the traditional ＂gene bits＂ in genetic algorithms is first replaced by ＂gene parameters＂, which could appear anywhere in GALS. A modeling procedure is taken to normalize the input data, and AL ＂tissue＂ is innovated to make AL more complex. GALS is anticipated to contribute significantly to the fitness of AL evolution. The formation of ＂tissue＂ begins with some different AL basic cells, and then tissue is produced by the casual selections of one or several of these cells. As a result, the gene parameters, represented by ＂tissues＂, could become highly diversified. This diversification should have obvious effects on improving gene fitness. This study took the innovative method of GALS in a stock forecasting problem under a carefully designed manipulating platform. And the researching results verify that the GALS is successful in improving the gene evolution fitness.展开更多
A networks-on-chip （NoC） cost-effective design method was given based on the globallyasynchronous locally-synchronous （GALS） interconnect structure. In this method, the synchronous mode was used to transmit data a...A networks-on-chip （NoC） cost-effective design method was given based on the globallyasynchronous locally-synchronous （GALS） interconnect structure. In this method, the synchronous mode was used to transmit data among routers, network interface （NI）, and intellectual property （IP） via a synchronous circuit. Compared with traditional methods of implementing GALS, this method greatly reduces the transmission latency and is compatible with existing very large scale integration （VLSI） design tools. The platform designed based on the method can support two kinds of packetizing mechanisms, any topology, several kinds of traffic, and many configurable parameters such as the number of virtual channels, thus the platform is universal. An NoC evaluation methodology is given with a case study showing that the platform and evaluation methodology work well.展开更多
This paper describes a circular first in first out （FIFO） and its protocols which have a very low latency while still maintaining high throughput. Unlike the existing serial FIFOs based on asynchronous micropipeline...This paper describes a circular first in first out （FIFO） and its protocols which have a very low latency while still maintaining high throughput. Unlike the existing serial FIFOs based on asynchronous micropipelines, this FIFO＇s cells communicate directly with the input and output ports through a common bus, which effectively eliminates the data movement from the input port to the output port, thereby reducing the latency and the power consumption. Furthermore, the latency does not increase with the number of FIFO stages. Single-track asynchronous protocols are used to simplify the FIFO controller design, with only three C-gates needed in each cell controller, which substantially reduces the area. Simulations with the TSMC 0.25 μm CMOS logic process show that the latency of the 4-stage FIFO is less than 581 ps and the throughput is higher than 2.2 GHz.展开更多
文摘In recent years, more attention has been paid on artificial life researches. Artificial life（AL） is a research on regulating gene parameters of digital organisms under complicated problematic environments through natural selections and evolutions to achieve the final emergence of intelligence. Most recent studies focused on solving certain real problems by artificial life methods, yet without much address on the AL life basic mechanism. The real problems are often very complicated, and the proposed methods sometimes seem too simple to handle those problems. This study proposed a new approach in AL research, named ＂generalized artificial life structure（GALS）＂, in which the traditional ＂gene bits＂ in genetic algorithms is first replaced by ＂gene parameters＂, which could appear anywhere in GALS. A modeling procedure is taken to normalize the input data, and AL ＂tissue＂ is innovated to make AL more complex. GALS is anticipated to contribute significantly to the fitness of AL evolution. The formation of ＂tissue＂ begins with some different AL basic cells, and then tissue is produced by the casual selections of one or several of these cells. As a result, the gene parameters, represented by ＂tissues＂, could become highly diversified. This diversification should have obvious effects on improving gene fitness. This study took the innovative method of GALS in a stock forecasting problem under a carefully designed manipulating platform. And the researching results verify that the GALS is successful in improving the gene evolution fitness.
基金Supported by the National Natural Science Foundation of China (No.90607009)the National High-Tech Research and Development(863) Program(No.2008AA01Z107)the National Key Basic Research and Development(973) Program of China(No.2007CB310701)
文摘A networks-on-chip （NoC） cost-effective design method was given based on the globallyasynchronous locally-synchronous （GALS） interconnect structure. In this method, the synchronous mode was used to transmit data among routers, network interface （NI）, and intellectual property （IP） via a synchronous circuit. Compared with traditional methods of implementing GALS, this method greatly reduces the transmission latency and is compatible with existing very large scale integration （VLSI） design tools. The platform designed based on the method can support two kinds of packetizing mechanisms, any topology, several kinds of traffic, and many configurable parameters such as the number of virtual channels, thus the platform is universal. An NoC evaluation methodology is given with a case study showing that the platform and evaluation methodology work well.
基金Supported by the National Key Basic Research and Development(973) Program of China (No. 2006CB302700)the National High-Tech Research and Development (863) Program of China (No.2007AA01Z2B3)
文摘This paper describes a circular first in first out （FIFO） and its protocols which have a very low latency while still maintaining high throughput. Unlike the existing serial FIFOs based on asynchronous micropipelines, this FIFO＇s cells communicate directly with the input and output ports through a common bus, which effectively eliminates the data movement from the input port to the output port, thereby reducing the latency and the power consumption. Furthermore, the latency does not increase with the number of FIFO stages. Single-track asynchronous protocols are used to simplify the FIFO controller design, with only three C-gates needed in each cell controller, which substantially reduces the area. Simulations with the TSMC 0.25 μm CMOS logic process show that the latency of the 4-stage FIFO is less than 581 ps and the throughput is higher than 2.2 GHz.
