Additive manufacturing(AM)is a free-form technology that shows great potential in the integrated creation of three-dimensional(3D)electronics.However,the fabrication of 3D conformal circuits that fulfill the requireme...Additive manufacturing(AM)is a free-form technology that shows great potential in the integrated creation of three-dimensional(3D)electronics.However,the fabrication of 3D conformal circuits that fulfill the requirements of high service temperature,high conductivity and high resolution remains a challenge.In this paper,a hybrid AM method combining the fused deposition modeling(FDM)and hydrophobic treatment assisted laser activation metallization(LAM)was proposed for manufacturing the polyetheretherketone(PEEK)-based 3D electronics,by which the conformal copper patterns were deposited on the 3D-printed PEEK parts,and the adhesion between them reached the 5B high level.Moreover,the 3D components could support the thermal cycling test from-55℃ to 125℃ for more than 100 cycles.Particularly,the application of a hydrophobic coating on the FDM-printed PEEK before LAM can promote an ideal catalytic selectivity on its surface,not affected by the inevitable printing borders and pores in the FDM-printed parts,then making the resolution of the electroless plated copper lines improved significantly.In consequence,Cu lines with width and spacing of only60μm and 100μm were obtained on both as-printed and after-polished PEEK substrates.Finally,the potential of this technique to fabricate 3D conformal electronics was demonstrated.展开更多
A 3D fan-out packaging method for the integration of 5G communication RF microsystem and antenna is studied.First of all,through the double-sided wiring technology on the glass wafer,the fabrication of 5G antenna arra...A 3D fan-out packaging method for the integration of 5G communication RF microsystem and antenna is studied.First of all,through the double-sided wiring technology on the glass wafer,the fabrication of 5G antenna array is realized.Then the low power devices such as through silicon via(TSV)transfer chips,filters and antenna tuners are flip-welded on the glass wafer,and the glass wafer is reformed into a wafer permanently bonded with glass and resin by the injection molding process with resin material.Finally,the thinning resin surface leaks out of the TSV transfer chip,the rewiring is carried out on the resin surface,and then the power amplifier,low-noise amplifier,power management and other devices are flip-welded on the resin wafer surface.A ball grid array(BGA)is implanted to form the final package.The loss of the RF transmission line is measured by using the RF millimeter wave probe table.The results show that the RF transmission loss from the chip end to the antenna end in the fan-out package is very small,and it is only 0.26 dB/mm when working in 60 GHz.A slot coupling antenna is designed on the glass wafer.The antenna can operate at 60 GHz and the maximum gain can reach 6 dB within the working bandwidth.This demonstration successfully provides a feasible solution for the 3D fan-out integration of RF microsystem and antenna in 5G communications.展开更多
Since 3D printed hard materials could match the shape of bone,cell survival and fate determination towards osteoblasts in such materials have become a popular research target.In this study,a scaffold of hardmaterial f...Since 3D printed hard materials could match the shape of bone,cell survival and fate determination towards osteoblasts in such materials have become a popular research target.In this study,a scaffold of hardmaterial for 3D fabrication was designed to regulate developmental signal(Notch)transduction guiding osteoblast differentiation.We established a polycaprolactone(PCL)and cell-integrated 3D printing system(PCI3D)to reciprocally print the beams of PCL and cell-laden hydrogel for a module.This PCI3D module holds good cell viability of over 87%,whereas cells show about sixfold proliferation in a 7-day culture.The osteocytic MLO-Y4 was engineered to overexpress Notch ligand Dll4,making up 25%after mixing with 75%stromal cells in the PCI3D module.Osteocytic Dll4,unlike other delta-like family members such as Dll1 or Dll3,promotes osteoblast differentiation and themineralization of primary mouse and a cell line of bone marrow stromal cells when cultured in a PCI3D module for up to 28 days.Mechanistically,osteocytic Dll4 could not promote osteogenic differentiation of the primary bone marrow stromal cells(BMSCs)after conditional deletion of the Notch transcription factor RBPjκby Cre recombinase.These data indicate that osteocytic Dll4 activates RBPjκ-dependent canonical Notch signaling in BMSCs for their oriented differentiation towards osteoblasts.Additionally,osteocytic Dll4 holds a great potential for angiogenesis in human umbilical vein endothelial cells within modules.Our study reveals that osteocytic Dll4 could be the osteogenic niche determining cell fate towards osteoblasts.This will open a new avenue to overcome the current limitation of poor cell viability and low bioactivity of traditional orthopedic implants.展开更多
Carbon nanotube field-effect transistors(CNT FETs)have been demonstrated to exhibit high performance only through low-temperature fabrication process and require a low thermal budget to construct monolithic three-dime...Carbon nanotube field-effect transistors(CNT FETs)have been demonstrated to exhibit high performance only through low-temperature fabrication process and require a low thermal budget to construct monolithic three-dimensional(M3D)integrated circuits(ICs),which have been considered a promising tech-nology to meet the demands of high-bandwidth computing and fully func-tional integration.However,the lack of high-quality CNT materials at the upper layer and a low-parasitic interlayer dielectric(ILD)makes the reported M3D CNT FETs and ICs unable to provide the predicted high performance.In this work,we demonstrate a multilayer stackable process for M3D integration of high-performance aligned carbon nanotube(A-CNT)transistors and ICs.A low-κ(-3)interlayer SiO_(2)layer is prepared from spin-on-glass(SOG)through processes with a highest temperature of 220℃,presenting low parasitic capaci-tance between two transistor layers and excellent planarization to offer an ideal surface for the A-CNT and device fabrication process.A high-quality A-CNT film with a carrier mobility of 650 cm 2 V^(-1)s^(-1)is prepared on the ILD layer through a clean transfer process,enabling the upper CNT FETs fabri-cated with a low-temperature process to exhibit high on-state current(1 mAμm^(-1))and peak transconductance(0.98 mSμm^(-1)).The bottom A-CNT FETs maintain pristine high performance after undergoing the ILD growth and upper FET fabrication.As a result,5-stage ring oscillators utilizing the M3D architecture show a gate propagation delay of 17 ps and an active region of approximately 100μm 2,representing the fastest and the most compact M3D ICs to date.展开更多
The resistive random access memory(RRAM)has stimulated a variety of promising applications including programmable analog circuit,massive data storage,neuromorphic computing,etc.These new emerging applications have hug...The resistive random access memory(RRAM)has stimulated a variety of promising applications including programmable analog circuit,massive data storage,neuromorphic computing,etc.These new emerging applications have huge demands on high integration density and low power consumption.The cross-point configuration or passive array,which offers the smallest footprint of cell size and feasible capability of multi-layer stacking,has received broad attention from the research community.In such array,correct operation of reading and writing on a cell relies on effective elimination of the sneaking current coming from the neighboring cells.This target requires nonlinear I-V characteristics of the memory cell,which can be realized by either adding separate selector or developing implicit build-in nonlinear cells.The performance of a passive array largely depends on the cell nonlinearity,reliability,on/off ratio,line resistance,thermal coupling,etc.This article provides a comprehensive review on the progress achieved concerning 3D RRAM integration.First,the authors start with a brief overview of the associative problems in passive array and the category of 3D architectures.Next,the state of the arts on the development of various selector devices and self-selective cells are presented.Key parameters that influence the device nonlinearity and current density are outlined according to the corresponding working principles.Then,the reliability issues in 3D array are summarized in terms of uniformity,endurance,retention,and disturbance.Subsequently,scaling issue and thermal crosstalk in 3D memory array are thoroughly discussed,and applications of 3D RRAM beyond storage,such as neuromorphic computing and CMOL circuit are discussed later.Summary and outlooks are given in the final.展开更多
The rational design of electrodes is the key to achieving ultrahigh-power performance in electrochemical energy storage devices.Recently,we have constructed well-organized and integrated three-dimensional(3D)carbon tu...The rational design of electrodes is the key to achieving ultrahigh-power performance in electrochemical energy storage devices.Recently,we have constructed well-organized and integrated three-dimensional(3D)carbon tube(CT)grids(3D-CTGs)using a 3D porous anodic aluminum oxide template-assisted method as electrodes of electrical double-layer capacitors(EDLCs),showing excellent frequency response performance.The unique design warrants fast ion migration channels,excellent electronic conductivity,and good structural stability.This study achieved one of the highest carbon-based ultrahigh-power EDLCs with the 3D-CTG electrodes,resulting in ultrahigh power of 437 and 1708 W·cm−3 with aqueous and organic electrolytes,respectively.Capacitors constructed with these electrodes would have important application prospects in the ultrahigh-power output.The rational design and fabrication of the 3D-CTGs electrodes have demonstrated their capability to build capacitors with ultrahighpower performance and open up new possibilities for applications requiring high-power output.展开更多
Interposers with through-silicon vias(TSVs)play a key role in the three-dimensional integration and packaging of integrated circuits and microelectromechanical systems.In the current practice of fabricating interposer...Interposers with through-silicon vias(TSVs)play a key role in the three-dimensional integration and packaging of integrated circuits and microelectromechanical systems.In the current practice of fabricating interposers,solder balls are placed next to the vias;however,this approach requires a large foot print for the input/output(I/O)connections.Therefore,in this study,we investigate the possibility of placing the solder balls directly on top of the vias,thereby enabling a smaller pitch between the solder balls and an increased density of the I/O connections.To reach this goal,inkjet printing(that is,piezo and super inkjet)was used to successfully fill and planarize hollow metal TSVs with a dielectric polymer.The under bump metallization(UBM)pads were also successfully printed with inkjet technology on top of the polymer-filled vias,using either Ag or Au inks.The reliability of the TSV interposers was investigated by a temperature cycling stress test(−40℃ to+125℃).The stress test showed no impact on DC resistance of the TSVs;however,shrinkage and delamination of the polymer was observed,along with some micro-cracks in the UBM pads.For proof of concept,SnAgCu-based solder balls were jetted on the UBM pads.展开更多
This article reviews advanced process and electron device technology of integrated circuits,including recent featuring progress and potential solutions for future development.In 5 years,for pushing the performance of ...This article reviews advanced process and electron device technology of integrated circuits,including recent featuring progress and potential solutions for future development.In 5 years,for pushing the performance of fin field-effect transistors(FinFET)to its limitations,several processes and device boosters are provided.Then,the three-dimensional(3 D)integration schemes with alternative materials and device architectures will pave paths for future technology evolution.Finally,it could be concluded that Moore’s law will undoubtedly continue in the next 15 years.展开更多
The majority of microelectromechanical system(MEMS)devices must be combined with integrated circuits(ICs)for operation in larger electronic systems.While MEMS transducers sense or control physical,optical or chemical ...The majority of microelectromechanical system(MEMS)devices must be combined with integrated circuits(ICs)for operation in larger electronic systems.While MEMS transducers sense or control physical,optical or chemical quantities,ICs typically provide functionalities related to the signals of these transducers,such as analog-to-digital conversion,amplification,filtering and information processing as well as communication between the MEMS transducer and the outside world.Thus,the vast majority of commercial MEMS products,such as accelerometers,gyroscopes and micro-mirror arrays,are integrated and packaged together with ICs.There are a variety of possible methods of integrating and packaging MEMS and IC components,and the technology of choice strongly depends on the device,the field of application and the commercial requirements.In this review paper,traditional as well as innovative and emerging approaches to MEMS and IC integration are reviewed.These include approaches based on the hybrid integration of multiple chips(multi-chip solutions)as well as system-on-chip solutions based on wafer-level monolithic integration and heterogeneous integration techniques.These are important technological building blocks for the‘More-Than-Moore’paradigm described in the International Technology Roadmap for Semiconductors.In this paper,the various approaches are categorized in a coherent manner,their merits are discussed,and suitable application areas and implementations are critically investigated.The implications of the different MEMS and IC integration approaches for packaging,testing and final system costs are reviewed.展开更多
基金supported by the National Natural Science Foundation of China(Grant No.51901082)the National Postdoctoral Program for Innovative Talents(BX20200137)the National Defense Basic Scientific Research Program of China(JCKY2018110C060)。
文摘Additive manufacturing(AM)is a free-form technology that shows great potential in the integrated creation of three-dimensional(3D)electronics.However,the fabrication of 3D conformal circuits that fulfill the requirements of high service temperature,high conductivity and high resolution remains a challenge.In this paper,a hybrid AM method combining the fused deposition modeling(FDM)and hydrophobic treatment assisted laser activation metallization(LAM)was proposed for manufacturing the polyetheretherketone(PEEK)-based 3D electronics,by which the conformal copper patterns were deposited on the 3D-printed PEEK parts,and the adhesion between them reached the 5B high level.Moreover,the 3D components could support the thermal cycling test from-55℃ to 125℃ for more than 100 cycles.Particularly,the application of a hydrophobic coating on the FDM-printed PEEK before LAM can promote an ideal catalytic selectivity on its surface,not affected by the inevitable printing borders and pores in the FDM-printed parts,then making the resolution of the electroless plated copper lines improved significantly.In consequence,Cu lines with width and spacing of only60μm and 100μm were obtained on both as-printed and after-polished PEEK substrates.Finally,the potential of this technique to fabricate 3D conformal electronics was demonstrated.
文摘A 3D fan-out packaging method for the integration of 5G communication RF microsystem and antenna is studied.First of all,through the double-sided wiring technology on the glass wafer,the fabrication of 5G antenna array is realized.Then the low power devices such as through silicon via(TSV)transfer chips,filters and antenna tuners are flip-welded on the glass wafer,and the glass wafer is reformed into a wafer permanently bonded with glass and resin by the injection molding process with resin material.Finally,the thinning resin surface leaks out of the TSV transfer chip,the rewiring is carried out on the resin surface,and then the power amplifier,low-noise amplifier,power management and other devices are flip-welded on the resin wafer surface.A ball grid array(BGA)is implanted to form the final package.The loss of the RF transmission line is measured by using the RF millimeter wave probe table.The results show that the RF transmission loss from the chip end to the antenna end in the fan-out package is very small,and it is only 0.26 dB/mm when working in 60 GHz.A slot coupling antenna is designed on the glass wafer.The antenna can operate at 60 GHz and the maximum gain can reach 6 dB within the working bandwidth.This demonstration successfully provides a feasible solution for the 3D fan-out integration of RF microsystem and antenna in 5G communications.
基金the National Natural Science Foundation of China(Nos.U1601220,82072450,and 81672118)Chongqing Science and Technology Commission-Basic Science and Frontier Technology Key Project(No.cstc2015jcyjBX0119)Chongqing Medical University Intelligent Medicine Research Project(No.ZHYX202115).
文摘Since 3D printed hard materials could match the shape of bone,cell survival and fate determination towards osteoblasts in such materials have become a popular research target.In this study,a scaffold of hardmaterial for 3D fabrication was designed to regulate developmental signal(Notch)transduction guiding osteoblast differentiation.We established a polycaprolactone(PCL)and cell-integrated 3D printing system(PCI3D)to reciprocally print the beams of PCL and cell-laden hydrogel for a module.This PCI3D module holds good cell viability of over 87%,whereas cells show about sixfold proliferation in a 7-day culture.The osteocytic MLO-Y4 was engineered to overexpress Notch ligand Dll4,making up 25%after mixing with 75%stromal cells in the PCI3D module.Osteocytic Dll4,unlike other delta-like family members such as Dll1 or Dll3,promotes osteoblast differentiation and themineralization of primary mouse and a cell line of bone marrow stromal cells when cultured in a PCI3D module for up to 28 days.Mechanistically,osteocytic Dll4 could not promote osteogenic differentiation of the primary bone marrow stromal cells(BMSCs)after conditional deletion of the Notch transcription factor RBPjκby Cre recombinase.These data indicate that osteocytic Dll4 activates RBPjκ-dependent canonical Notch signaling in BMSCs for their oriented differentiation towards osteoblasts.Additionally,osteocytic Dll4 holds a great potential for angiogenesis in human umbilical vein endothelial cells within modules.Our study reveals that osteocytic Dll4 could be the osteogenic niche determining cell fate towards osteoblasts.This will open a new avenue to overcome the current limitation of poor cell viability and low bioactivity of traditional orthopedic implants.
基金National Key Research&Development Program,Grant/Award Number:2022YFB4401601Natural Science Foundation of China,Grant/Award Number:62225101Beijing Municipal Science and Technology Commission,Grant/Award Number:Z191100007019001-3。
文摘Carbon nanotube field-effect transistors(CNT FETs)have been demonstrated to exhibit high performance only through low-temperature fabrication process and require a low thermal budget to construct monolithic three-dimensional(M3D)integrated circuits(ICs),which have been considered a promising tech-nology to meet the demands of high-bandwidth computing and fully func-tional integration.However,the lack of high-quality CNT materials at the upper layer and a low-parasitic interlayer dielectric(ILD)makes the reported M3D CNT FETs and ICs unable to provide the predicted high performance.In this work,we demonstrate a multilayer stackable process for M3D integration of high-performance aligned carbon nanotube(A-CNT)transistors and ICs.A low-κ(-3)interlayer SiO_(2)layer is prepared from spin-on-glass(SOG)through processes with a highest temperature of 220℃,presenting low parasitic capaci-tance between two transistor layers and excellent planarization to offer an ideal surface for the A-CNT and device fabrication process.A high-quality A-CNT film with a carrier mobility of 650 cm 2 V^(-1)s^(-1)is prepared on the ILD layer through a clean transfer process,enabling the upper CNT FETs fabri-cated with a low-temperature process to exhibit high on-state current(1 mAμm^(-1))and peak transconductance(0.98 mSμm^(-1)).The bottom A-CNT FETs maintain pristine high performance after undergoing the ILD growth and upper FET fabrication.As a result,5-stage ring oscillators utilizing the M3D architecture show a gate propagation delay of 17 ps and an active region of approximately 100μm 2,representing the fastest and the most compact M3D ICs to date.
基金the National Key R&D Program of China(Grant Nos.2018YFB0407501 and 2016YFA0201800)the National Natural Science Foundation of China(Grant Nos.61804173,61922083,61804167,61904200,and 61821091)the fourth China Association for Science and Technology Youth Talent Support Project(Grant No.2019QNRC001).
文摘The resistive random access memory(RRAM)has stimulated a variety of promising applications including programmable analog circuit,massive data storage,neuromorphic computing,etc.These new emerging applications have huge demands on high integration density and low power consumption.The cross-point configuration or passive array,which offers the smallest footprint of cell size and feasible capability of multi-layer stacking,has received broad attention from the research community.In such array,correct operation of reading and writing on a cell relies on effective elimination of the sneaking current coming from the neighboring cells.This target requires nonlinear I-V characteristics of the memory cell,which can be realized by either adding separate selector or developing implicit build-in nonlinear cells.The performance of a passive array largely depends on the cell nonlinearity,reliability,on/off ratio,line resistance,thermal coupling,etc.This article provides a comprehensive review on the progress achieved concerning 3D RRAM integration.First,the authors start with a brief overview of the associative problems in passive array and the category of 3D architectures.Next,the state of the arts on the development of various selector devices and self-selective cells are presented.Key parameters that influence the device nonlinearity and current density are outlined according to the corresponding working principles.Then,the reliability issues in 3D array are summarized in terms of uniformity,endurance,retention,and disturbance.Subsequently,scaling issue and thermal crosstalk in 3D memory array are thoroughly discussed,and applications of 3D RRAM beyond storage,such as neuromorphic computing and CMOL circuit are discussed later.Summary and outlooks are given in the final.
基金supported by the National Natural Science Foundation of China(Nos.91963202,52072372,and 52232007).
文摘The rational design of electrodes is the key to achieving ultrahigh-power performance in electrochemical energy storage devices.Recently,we have constructed well-organized and integrated three-dimensional(3D)carbon tube(CT)grids(3D-CTGs)using a 3D porous anodic aluminum oxide template-assisted method as electrodes of electrical double-layer capacitors(EDLCs),showing excellent frequency response performance.The unique design warrants fast ion migration channels,excellent electronic conductivity,and good structural stability.This study achieved one of the highest carbon-based ultrahigh-power EDLCs with the 3D-CTG electrodes,resulting in ultrahigh power of 437 and 1708 W·cm−3 with aqueous and organic electrolytes,respectively.Capacitors constructed with these electrodes would have important application prospects in the ultrahigh-power output.The rational design and fabrication of the 3D-CTGs electrodes have demonstrated their capability to build capacitors with ultrahighpower performance and open up new possibilities for applications requiring high-power output.
基金This work is supported by ENIAC-JU Project Prominent Grant No 324189 and Tekes Grant No.40336/12 and Vinnova Grants Nos.2012-04301,2012-04287,and 2012-04314MM is supported by the Academy of Finland Grant Nos.288945 and 294119The work of Silex and KTH was funded in part through an Industrial Ph.D.grant from the Swedish Foundation for Strategic Research(SSF),Grant No.ID14-0033.
文摘Interposers with through-silicon vias(TSVs)play a key role in the three-dimensional integration and packaging of integrated circuits and microelectromechanical systems.In the current practice of fabricating interposers,solder balls are placed next to the vias;however,this approach requires a large foot print for the input/output(I/O)connections.Therefore,in this study,we investigate the possibility of placing the solder balls directly on top of the vias,thereby enabling a smaller pitch between the solder balls and an increased density of the I/O connections.To reach this goal,inkjet printing(that is,piezo and super inkjet)was used to successfully fill and planarize hollow metal TSVs with a dielectric polymer.The under bump metallization(UBM)pads were also successfully printed with inkjet technology on top of the polymer-filled vias,using either Ag or Au inks.The reliability of the TSV interposers was investigated by a temperature cycling stress test(−40℃ to+125℃).The stress test showed no impact on DC resistance of the TSVs;however,shrinkage and delamination of the polymer was observed,along with some micro-cracks in the UBM pads.For proof of concept,SnAgCu-based solder balls were jetted on the UBM pads.
基金the support from the members of Integrated Circuit Advanced Process R&D Center,Institute of Microelectronics,Chinese Academy of Sciencessupported in part by the National Key Project of Science and Technology of China(No.2017ZX02315001-002)。
文摘This article reviews advanced process and electron device technology of integrated circuits,including recent featuring progress and potential solutions for future development.In 5 years,for pushing the performance of fin field-effect transistors(FinFET)to its limitations,several processes and device boosters are provided.Then,the three-dimensional(3 D)integration schemes with alternative materials and device architectures will pave paths for future technology evolution.Finally,it could be concluded that Moore’s law will undoubtedly continue in the next 15 years.
基金The work was partially funded by the Swedish Research Council,by the European 7^(th)Framework Programme under grant agreement FP7-NEMIAC(No.288670)by the European Research Council through the ERC Advanced Grant xMEMs(No.267528)and the ERC Starting Grant M&M’s(No.277879).
文摘The majority of microelectromechanical system(MEMS)devices must be combined with integrated circuits(ICs)for operation in larger electronic systems.While MEMS transducers sense or control physical,optical or chemical quantities,ICs typically provide functionalities related to the signals of these transducers,such as analog-to-digital conversion,amplification,filtering and information processing as well as communication between the MEMS transducer and the outside world.Thus,the vast majority of commercial MEMS products,such as accelerometers,gyroscopes and micro-mirror arrays,are integrated and packaged together with ICs.There are a variety of possible methods of integrating and packaging MEMS and IC components,and the technology of choice strongly depends on the device,the field of application and the commercial requirements.In this review paper,traditional as well as innovative and emerging approaches to MEMS and IC integration are reviewed.These include approaches based on the hybrid integration of multiple chips(multi-chip solutions)as well as system-on-chip solutions based on wafer-level monolithic integration and heterogeneous integration techniques.These are important technological building blocks for the‘More-Than-Moore’paradigm described in the International Technology Roadmap for Semiconductors.In this paper,the various approaches are categorized in a coherent manner,their merits are discussed,and suitable application areas and implementations are critically investigated.The implications of the different MEMS and IC integration approaches for packaging,testing and final system costs are reviewed.
