In the DC microgrid,the lack of inertia and damping in power electronic converters results in poor stability of DC bus voltage and low inertia of the DC microgrid during fluctuations in load and photovoltaic power.To ...In the DC microgrid,the lack of inertia and damping in power electronic converters results in poor stability of DC bus voltage and low inertia of the DC microgrid during fluctuations in load and photovoltaic power.To address this issue,the application of a virtual synchronous generator(VSG)in grid-connected inverters control is referenced and proposes a control strategy called the analogous virtual synchronous generator(AVSG)control strategy for the interface DC/DC converter of the battery in the microgrid.Besides,a flexible parameter adaptive control method is introduced to further enhance the inertial behavior of the AVSG control.Firstly,a theoretical analysis is conducted on the various components of the DC microgrid,the structure of analogous virtual synchronous generator,and the control structure’s main parameters related to the DC microgrid’s inertial behavior.Secondly,the voltage change rate tracking coefficient is introduced to adjust the change of the virtual capacitance and damping coefficient flexibility,which further strengthens the inertia trend of the DC microgrid.Additionally,a small-signal modeling approach is used to analyze the approximate range of the AVSG’s main parameters ensuring system stability.Finally,conduct a simulation analysis by building the model of the DC microgrid system with photovoltaic(PV)and battery energy storage(BES)in MATLAB/Simulink.Simulation results from different scenarios have verified that the AVSG control introduces fixed inertia and damping into the droop control of the battery,resulting in a certain level of inertia enhancement.Furthermore,the additional adaptive control strategy built upon the AVSG control provides better and flexible inertial support for the DC microgrid,further enhances the stability of the DC bus voltage,and has a more positive impact on the battery performance.展开更多
As deep learning techniques such as Convolutional Neural Networks(CNNs)are widely adopted,the complexity of CNNs is rapidly increasing due to the growing demand for CNN accelerator system-on-chip(SoC).Although convent...As deep learning techniques such as Convolutional Neural Networks(CNNs)are widely adopted,the complexity of CNNs is rapidly increasing due to the growing demand for CNN accelerator system-on-chip(SoC).Although conventional CNN accelerators can reduce the computational time of learning and inference tasks,they tend to occupy large chip areas due to many multiply-and-accumulate(MAC)operators when implemented in complex digital circuits,incurring excessive power consumption.To overcome these drawbacks,this work implements an analog convolutional filter consisting of an analog multiply-and-accumulate arithmetic circuit along with an analog-to-digital converter(ADC).This paper introduces the architecture of an analog convolutional kernel comprised of low-power ultra-small circuits for neural network accelerator chips.ADC is an essential component of the analog convolutional kernel used to convert the analog convolutional result to digital values to be stored in memory.This work presents the implementation of a highly low-power and area-efficient 12-bit Successive Approximation Register(SAR)ADC.Unlink most other SAR-ADCs with differential structure;the proposed ADC employs a single-ended capacitor array to support the preceding single-ended max-pooling circuit along with minimal power consumption.The SARADCimplementation also introduces a unique circuit that reduces kick-back noise to increase performance.It was implemented in a test chip using a 55 nm CMOS process.It demonstrates that the proposed ADC reduces Kick-back noise by 40%and consequently improves the ADC’s resolution by about 10%while providing a near rail-to-rail dynamic rangewith significantly lower power consumption than conventional ADCs.The ADC test chip shows a chip size of 4600μm^(2)with a power consumption of 6.6μW while providing an signal-to-noise-and-distortion ratio(SNDR)of 68.45 dB,corresponding to an effective number of bits(ENOB)of 11.07 bits.展开更多
This article presents an integrated current mode configurable analog block(CAB)system for field-programmable analog array(FPAA).The proposed architecture is based on the complementary metal-oxide semiconductor(CMOS)tr...This article presents an integrated current mode configurable analog block(CAB)system for field-programmable analog array(FPAA).The proposed architecture is based on the complementary metal-oxide semiconductor(CMOS)transistor level design where MOSFET transistors operating in the saturation region are adopted.The proposed CAB architecture is designed to implement six of thewidely used current mode operations in analog processing systems:addition,subtraction,integration,multiplication,division,and pass operation.The functionality of the proposed CAB is demonstrated through these six operations,where each operation is chosen based on the user’s selection in the CAB interface system.The architecture of the CAB system proposes an optimized way of designing and integrating only three functional cells with the interface circuitry to achieve the six operations.Furthermore,optimized programming and digital tuning circuitry are implemented in the architecture to control and interface with the functional cells.Moreover,these designed programming and tuning circuitries play an essential role in optimizing the performance of the proposed design.Simulation of the proposed CMOS Transistor Based CAB system is carried out using Tanner EDA Tools in 0.35μm standard CMOS technology.The design uses a±1.5 V power supply and results in maximum 3 dB bandwidth of 34.9 MHz and an approximate size of 0.0537 mm2.This demonstrates the advantages of the design over the current state-of-the-art designs presented for comparison in this article.Consequently,the proposed design has a clear aspect of simplicity,low power consumption,and high bandwidth operation,which makes it a suitable candidate for mobile telecommunications applications.展开更多
The Kuqa fold-and-thrust belt exhibits apparent structural variation in the western and eastern zone.Two salt layer act as effective decollements and influence the varied deformation.In this study,detailed seismic int...The Kuqa fold-and-thrust belt exhibits apparent structural variation in the western and eastern zone.Two salt layer act as effective decollements and influence the varied deformation.In this study,detailed seismic interpretations and analog modeling are presented to construct the suprasalt and subsalt structures in the transfer zone of the middle Kuqa and investigate the influence of the two salt layers.The results reveal that the relationship of the two salt layers changes from separated to connected,and then overlapped toward the foreland in the transfer zone.Different structural models are formed in the suprasalt and subsalt units due to the interaction of the two salt layers.The imbricate thrust faults form two broom-like fault systems in the subsalt units.The suprasalt units develop detached folds terminating toward the east in the region near the orogenic belt.Whereas,two offset anticlines with different trends develop at the frontal edge of the lower salt layer and the trailing edge of the upper salt layer,respectively.According to exploration results in this region,the relationship between suprasalt and subsalt structures has an influence on hydrocarbon accumulation.We believe that the connected deformation contains high-risk plays while the decoupled deformation contains well-preserved plays.展开更多
This manuscript explores the behavior of a junctionless tri-gate FinFET at the nano-scale region using SiGe material for the channel.For the analysis,three different channel structures are used:(a)tri-layer stack chan...This manuscript explores the behavior of a junctionless tri-gate FinFET at the nano-scale region using SiGe material for the channel.For the analysis,three different channel structures are used:(a)tri-layer stack channel(TLSC)(Si-SiGe-Si),(b)double layer stack channel(DLSC)(SiGe-Si),(c)single layer channel(SLC)(S_(i)).The I−V characteristics,subthreshold swing(SS),drain-induced barrier lowering(DIBL),threshold voltage(V_(t)),drain current(ION),OFF current(IOFF),and ON-OFF current ratio(ION/IOFF)are observed for the structures at a 20 nm gate length.It is seen that TLSC provides 21.3%and 14.3%more ON current than DLSC and SLC,respectively.The paper also explores the analog and RF factors such as input transconductance(g_(m)),output transconductance(gds),gain(gm/gds),transconductance generation factor(TGF),cut-off frequency(f_(T)),maximum oscillation frequency(f_(max)),gain frequency product(GFP)and linearity performance parameters such as second and third-order harmonics(g_(m2),g_(m3)),voltage intercept points(VIP_(2),VIP_(3))and 1-dB compression points for the three structures.The results show that the TLSC has a high analog performance due to more gm and provides 16.3%,48.4%more gain than SLC and DLSC,respectively and it also provides better linearity.All the results are obtained using the VisualTCAD tool.展开更多
At present,deep learning has been well applied in many fields.However,due to the high complexity of hypothesis space,numerous training samples are usually required to ensure the reliability of minimizing experience ri...At present,deep learning has been well applied in many fields.However,due to the high complexity of hypothesis space,numerous training samples are usually required to ensure the reliability of minimizing experience risk.Therefore,training a classifier with a small number of training examples is a challenging task.From a biological point of view,based on the assumption that rich prior knowledge and analogical association should enable human beings to quickly distinguish novel things from a few or even one example,we proposed a dynamic analogical association algorithm to make the model use only a few labeled samples for classification.To be specific,the algorithm search for knowledge structures similar to existing tasks in prior knowledge based on manifold matching,and combine sampling distributions to generate offsets instead of two sample points,thereby ensuring high confidence and significant contribution to the classification.The comparative results on two common benchmark datasets substantiate the superiority of the proposed method compared to existing data generation approaches for few-shot learning,and the effectiveness of the algorithm has been proved through ablation experiments.展开更多
With the continuous development of science and technology, digital signal processing is more and more widely used in various fields. Among them, the analog-to-digital converter (ADC) is one of the key components to co...With the continuous development of science and technology, digital signal processing is more and more widely used in various fields. Among them, the analog-to-digital converter (ADC) is one of the key components to convert analog signals to digital signals. As a common type of ADC, 12-bit sequential approximation analog-to-digital converter (SAR ADC) has attracted extensive attention for its performance and application. This paper aims to conduct in-depth research and analysis of 12-bit SAR ADC to meet the growing demands of digital signal processing. This article designs a 12-bit, successive approximation analog-to-digital converter (SAR ADC) with a sampling rate of 5 MS/s. The overall circuit adopts a fully differential structure, with key modules including DAC capacitor array, comparator, and control logic. According to the DAC circuit in this paper, a fully differential capacitor DAC array structure is proposed to reduce the area of layout DAC. The comparator uses a digital dynamic comparator to improve the ADC conversion speed. The chip is designed based on the SMIC180 nm CMOS process. The simulation results show that when the sampling rate is 5 MS/s, the effective bit of SAR ADC is 11.92 bit, the SNR is 74.62 dB, and the SFDR is 89.24 dB.展开更多
The authors use numerical model integral products in a third level forecast of synthetically multi-level analog forecast technology.This is one of the strongest points of this study,which also includes the re-ducing m...The authors use numerical model integral products in a third level forecast of synthetically multi-level analog forecast technology.This is one of the strongest points of this study,which also includes the re-ducing mean vacant-forecast rate method,which pos-sesses many advantages with regard to filtering the analog term.Moreover,the similitude degree between samples is assessed using a combination of meteorological elements,which works better than that described using a single element in earlier analog forecast studies.Based on these techniques,the authors apply the model output,air sounding,surface observation and weather map data from 1990 to 2002 to perform an analog experiment of the quasi-stationary front rainstorm.The most important re-sults are as follows:(1) The forecast successful index is 0.36,and was improved after the forecast model was re-vised.(2) The forecast precise rate (0.59) and the lost-forecast rate (0.33) are also better than those of other methods.(3) Based on the model output data,the syn-thetically multilevel analog forecast technology can pro-duce more accurate forecasts of a quasi-stationary front rainstorm.(4) Optimal analog elements reveal that trig-gering mechanisms are located in the lower troposphere while upper level systems are more important in main-taining the phase of the rainstorm.These variables should be first taken into account in operational forecasts of the quasi-stationary front rainstorm.(5) In addition,experi-ments reveal that the position of the key zone is mainly decided by the position of the system causing the heavy rainfall.展开更多
The drive towards shorter design cycles for analog integrated circuits has given impetus to the development of Field Programmable Analog Arrays(FPAAs),which are the analogue counterparts of Field Programmable Gate Arr...The drive towards shorter design cycles for analog integrated circuits has given impetus to the development of Field Programmable Analog Arrays(FPAAs),which are the analogue counterparts of Field Programmable Gate Arrays(FPGAs).In this paper,we present a new design methodology which using FPAA as a powerful analog front-end processing platform in the smart sensory microsystem.The proposed FPAA contains 16 homogeneous mixed-grained Configurable Analog Blocks(CABs) which house a variety of processing elements especially the proposed fine-grained Core Configurable Amplifiers(CCAs).The high flexible CABs allow the FPAA operating in both continuous-time and discrete-time approaches suitable to support variety of sensors.To reduce the nonideal parasitic effects and save area,the fat-tree interconnection network is adopted in this FPAA.The functionality of this FPAA is demonstrated through embedding of voltage and capacitive sensor signal readout circuits and a configurable band pass filter.The minimal detectable voltage and capacitor achieves 38 uV and 8.3 aF respectively within 100 Hz sensor bandwidth.The power consumption comparison of CCA in three applications shows that the FPAA has high power efficiency.And the simulation results also show that the FPAA has good tolerance with wide PVT variations.展开更多
A micro-extended-analog-computer(uEAC)is developed on the basis of Rubel's extended analog computer(EAC)model.Through the uEAC mathematical model,the resistance properties of the conductive sheet,several feedback ...A micro-extended-analog-computer(uEAC)is developed on the basis of Rubel's extended analog computer(EAC)model.Through the uEAC mathematical model,the resistance properties of the conductive sheet,several feedback uEAC models,and a more flexible uEAC cell structure with a multilevel hierarchy are discussed.Futhermore,for the dynamic uEAC array with a linear Lukasiewicz function,a nonlinear differential equation description is presented,and then a sufficient global asymptotic stability condition is derived by utilizing a Lyapunov function and a Lipchitz function.Finally,comparative simulations for a cam servo mechanism system are conducted to verify the capability of the uEAC array as an adaptive controller.展开更多
As a method of logical thinking,analogical inference has a long history both in ancient Greece and in the ancient East,and has been widely used in the daily life.Even today it still plays an important role in understa...As a method of logical thinking,analogical inference has a long history both in ancient Greece and in the ancient East,and has been widely used in the daily life.Even today it still plays an important role in understanding and improving the world.Particularly,its cognitive function is not only reflected in the interpretation and further understanding of the existing knowledge,but more importantly,it can still improve our scientific level,expand our cognitive field,and help us open up the unknown field.That,of course,is where its innovation lies.From the perspective of analogical inference,its innovative function should be based on the identical or at least the similar relationship between the things.In addition,it should also be based on the ability of imagination played by the cognition subject.展开更多
We considered the physiological mechanisms of functioning of the retina’s neural network. It is marked that the primary function of a neural network is an analog-to-digital conversion of the receptor potential of pho...We considered the physiological mechanisms of functioning of the retina’s neural network. It is marked that the primary function of a neural network is an analog-to-digital conversion of the receptor potential of photoreceptor into the pulse-to-digital signal to ganglion cells. We showed the role of different types of neurons in the work of analog-to-digital converter. We gave the equivalent circuit of this converter. We researched the mechanism of the numeric coding of the receptor potential of the photoreceptor.展开更多
New voltage-controlled floating inductors employing CFOAs and an analog multiplier have been presented which have the attractive features of using a canonic number of passive components (only two resistors and a capac...New voltage-controlled floating inductors employing CFOAs and an analog multiplier have been presented which have the attractive features of using a canonic number of passive components (only two resistors and a capacitor) and not requiring any component-matching conditions and design constraints for the intended type of inductance realization. The workability and applications of the new circuits have been demonstrated by SPICE simulation and hardware experimental results based upon AD844-type CFOAs and AD633-type/MPY534 type analog multipliers.展开更多
This paper proposes novel floating-gate MOSFET (FGMOS) based Voltage Buffer, Analog Inverter and Winner-Take-All (WTA) circuits. The proposed circuits have low power dissipation. All proposed circuits are simulated us...This paper proposes novel floating-gate MOSFET (FGMOS) based Voltage Buffer, Analog Inverter and Winner-Take-All (WTA) circuits. The proposed circuits have low power dissipation. All proposed circuits are simulated using SPICE in 180 nm CMOS technology with supply voltages of ±1.25 V. The simulation results demonstrate increase in input range for FGMOS based voltage buffer and analog inverter and maximum power dissipation of 0.5 mW, 1.9 mW and 0.429 mW for FGMOS based voltage buffer, analog inverter and WTA circuits, respectively. The proposed circuits are intended to find applications in low voltage, low power consumer electronics.展开更多
BACKGROUND Nucleos(t)ide analog(NA)has shown limited effectiveness against hepatitis B surface antigen(HBsAg)clearance in chronic hepatitis B(CHB)patients.AIM To evaluate the efficacy and safety of add-on peginterfero...BACKGROUND Nucleos(t)ide analog(NA)has shown limited effectiveness against hepatitis B surface antigen(HBsAg)clearance in chronic hepatitis B(CHB)patients.AIM To evaluate the efficacy and safety of add-on peginterferonα-2a(peg-IFNα-2a)to an ongoing NA regimen in CHB patients.METHODS In this observational study,195 CHB patients with HBsAg≤1500 IU/m L,hepatitis B e antigen(HBeAg)-negative(including HBeAg-negative patients or HBeAg-positive patients who achieved HBeAg-negative after antiviral treatment with NA)and hepatitis B virus-deoxyribonucleic acid<1.0×10^2 IU/mL after over 1 year of NA therapy were enrolled between November 2015 and December2018 at the Second Affiliated Hospital of Xi'an Jiaotong University,China.Patients were given the choice between receiving either peg-IFNα-2a add-on therapy to an ongoing NA regimen(add-on group,n=91)or continuous NA monotherapy(monotherapy group,n=104)after being informed of the benefits and risks of the peg-IFNα-2a therapy.Total therapy duration of peg-IFNα-2a was 48 wk.All patients were followed-up to week 72(24 wk after discontinuation of peg-IFNα-2a).The primary endpoint was the proportion of patients with HBsAg clearance at week 72.RESULTS Demographic and baseline characteristics were comparable between the two groups.Intention-to-treatment analysis showed that the HBsAg clearance rate in the add-on group and monotherapy group was 37.4%(34/91)and 1.9%(2/104)at week 72,respectively.The HBsAg seroconversion rate in the add-on group was 29.7%(27/91)at week 72,and no patient in the monotherapy group achieved HBsAg seroconversion at week 72.The HBsAg clearance and seroconversion rates in the add-on group were significantly higher than in the monotherapy group at week 72(P<0.001).Younger patients,lower baseline HBsAg concentration,lower HBsAg concentrations at weeks 12 and 24,greater HBsAg decline from baseline to weeks 12 and 24 and the alanine aminotransferase≥2×upper limit of normal during the first 12 wk of therapy were strong predictors of HBsAg clearance in patients with peg-IFNα-2a add-on treatment.Regarding the safety of the treatment,4.4%(4/91)of patients in the add-on group discontinued peg-IFNα-2a due to adverse events.No severe adverse events were noted.CONCLUSION Peg-IFNα-2a as an add-on therapy augments HBsAg clearance in HBeAg-negative CHB patients with HBsAg≤1500 IU/m L after over 1 year of NA therapy.展开更多
基金funded by the National Natural Science Foundation of China(52067013),and the Provincial Natural Science Foundation of Gansu(20JR5RA395).
文摘In the DC microgrid,the lack of inertia and damping in power electronic converters results in poor stability of DC bus voltage and low inertia of the DC microgrid during fluctuations in load and photovoltaic power.To address this issue,the application of a virtual synchronous generator(VSG)in grid-connected inverters control is referenced and proposes a control strategy called the analogous virtual synchronous generator(AVSG)control strategy for the interface DC/DC converter of the battery in the microgrid.Besides,a flexible parameter adaptive control method is introduced to further enhance the inertial behavior of the AVSG control.Firstly,a theoretical analysis is conducted on the various components of the DC microgrid,the structure of analogous virtual synchronous generator,and the control structure’s main parameters related to the DC microgrid’s inertial behavior.Secondly,the voltage change rate tracking coefficient is introduced to adjust the change of the virtual capacitance and damping coefficient flexibility,which further strengthens the inertia trend of the DC microgrid.Additionally,a small-signal modeling approach is used to analyze the approximate range of the AVSG’s main parameters ensuring system stability.Finally,conduct a simulation analysis by building the model of the DC microgrid system with photovoltaic(PV)and battery energy storage(BES)in MATLAB/Simulink.Simulation results from different scenarios have verified that the AVSG control introduces fixed inertia and damping into the droop control of the battery,resulting in a certain level of inertia enhancement.Furthermore,the additional adaptive control strategy built upon the AVSG control provides better and flexible inertial support for the DC microgrid,further enhances the stability of the DC bus voltage,and has a more positive impact on the battery performance.
基金This work was supported by the National Research Foundation of Korea(NRF)grant funded by theKorea government(MSIT)(No.2022R1A5A8026986)and supported by Institute of Information&communications Technology Planning&Evaluation(IITP)grant funded by the Korea government(MSIT)(No.2020-0-01304,Development of Self-learnable Mobile Recursive Neural Network Processor Technology)+3 种基金It was also supported by the MSIT(Ministry of Science and ICT),Korea,under the Grand Information Technology Research Center support program(IITP-2022-2020-0-01462)supervised by the“IITP(Institute for Information&communications Technology Planning&Evaluation)”supported by the National Research Foundation of Korea(NRF)grant funded by the Korea government(MSIT)(No.2021R1F1A1061314)In addition,this work was conducted during the research year of Chungbuk National University in 2020.
文摘As deep learning techniques such as Convolutional Neural Networks(CNNs)are widely adopted,the complexity of CNNs is rapidly increasing due to the growing demand for CNN accelerator system-on-chip(SoC).Although conventional CNN accelerators can reduce the computational time of learning and inference tasks,they tend to occupy large chip areas due to many multiply-and-accumulate(MAC)operators when implemented in complex digital circuits,incurring excessive power consumption.To overcome these drawbacks,this work implements an analog convolutional filter consisting of an analog multiply-and-accumulate arithmetic circuit along with an analog-to-digital converter(ADC).This paper introduces the architecture of an analog convolutional kernel comprised of low-power ultra-small circuits for neural network accelerator chips.ADC is an essential component of the analog convolutional kernel used to convert the analog convolutional result to digital values to be stored in memory.This work presents the implementation of a highly low-power and area-efficient 12-bit Successive Approximation Register(SAR)ADC.Unlink most other SAR-ADCs with differential structure;the proposed ADC employs a single-ended capacitor array to support the preceding single-ended max-pooling circuit along with minimal power consumption.The SARADCimplementation also introduces a unique circuit that reduces kick-back noise to increase performance.It was implemented in a test chip using a 55 nm CMOS process.It demonstrates that the proposed ADC reduces Kick-back noise by 40%and consequently improves the ADC’s resolution by about 10%while providing a near rail-to-rail dynamic rangewith significantly lower power consumption than conventional ADCs.The ADC test chip shows a chip size of 4600μm^(2)with a power consumption of 6.6μW while providing an signal-to-noise-and-distortion ratio(SNDR)of 68.45 dB,corresponding to an effective number of bits(ENOB)of 11.07 bits.
基金This work was supported in part by the Geran Galakan Penyelidik Muda Grant(GGPM),Universiti Kebangsaan Malaysia,Selangor,Malaysia under grant GGPM-2021-055.
文摘This article presents an integrated current mode configurable analog block(CAB)system for field-programmable analog array(FPAA).The proposed architecture is based on the complementary metal-oxide semiconductor(CMOS)transistor level design where MOSFET transistors operating in the saturation region are adopted.The proposed CAB architecture is designed to implement six of thewidely used current mode operations in analog processing systems:addition,subtraction,integration,multiplication,division,and pass operation.The functionality of the proposed CAB is demonstrated through these six operations,where each operation is chosen based on the user’s selection in the CAB interface system.The architecture of the CAB system proposes an optimized way of designing and integrating only three functional cells with the interface circuitry to achieve the six operations.Furthermore,optimized programming and digital tuning circuitry are implemented in the architecture to control and interface with the functional cells.Moreover,these designed programming and tuning circuitries play an essential role in optimizing the performance of the proposed design.Simulation of the proposed CMOS Transistor Based CAB system is carried out using Tanner EDA Tools in 0.35μm standard CMOS technology.The design uses a±1.5 V power supply and results in maximum 3 dB bandwidth of 34.9 MHz and an approximate size of 0.0537 mm2.This demonstrates the advantages of the design over the current state-of-the-art designs presented for comparison in this article.Consequently,the proposed design has a clear aspect of simplicity,low power consumption,and high bandwidth operation,which makes it a suitable candidate for mobile telecommunications applications.
基金supported by the National Natural Science Foundation of China(Grant Nos.41572187,41972219,41927802 and 42072320)the China Postdoctoral Science Foundation(Grant No.2020M671432)。
文摘The Kuqa fold-and-thrust belt exhibits apparent structural variation in the western and eastern zone.Two salt layer act as effective decollements and influence the varied deformation.In this study,detailed seismic interpretations and analog modeling are presented to construct the suprasalt and subsalt structures in the transfer zone of the middle Kuqa and investigate the influence of the two salt layers.The results reveal that the relationship of the two salt layers changes from separated to connected,and then overlapped toward the foreland in the transfer zone.Different structural models are formed in the suprasalt and subsalt units due to the interaction of the two salt layers.The imbricate thrust faults form two broom-like fault systems in the subsalt units.The suprasalt units develop detached folds terminating toward the east in the region near the orogenic belt.Whereas,two offset anticlines with different trends develop at the frontal edge of the lower salt layer and the trailing edge of the upper salt layer,respectively.According to exploration results in this region,the relationship between suprasalt and subsalt structures has an influence on hydrocarbon accumulation.We believe that the connected deformation contains high-risk plays while the decoupled deformation contains well-preserved plays.
文摘This manuscript explores the behavior of a junctionless tri-gate FinFET at the nano-scale region using SiGe material for the channel.For the analysis,three different channel structures are used:(a)tri-layer stack channel(TLSC)(Si-SiGe-Si),(b)double layer stack channel(DLSC)(SiGe-Si),(c)single layer channel(SLC)(S_(i)).The I−V characteristics,subthreshold swing(SS),drain-induced barrier lowering(DIBL),threshold voltage(V_(t)),drain current(ION),OFF current(IOFF),and ON-OFF current ratio(ION/IOFF)are observed for the structures at a 20 nm gate length.It is seen that TLSC provides 21.3%and 14.3%more ON current than DLSC and SLC,respectively.The paper also explores the analog and RF factors such as input transconductance(g_(m)),output transconductance(gds),gain(gm/gds),transconductance generation factor(TGF),cut-off frequency(f_(T)),maximum oscillation frequency(f_(max)),gain frequency product(GFP)and linearity performance parameters such as second and third-order harmonics(g_(m2),g_(m3)),voltage intercept points(VIP_(2),VIP_(3))and 1-dB compression points for the three structures.The results show that the TLSC has a high analog performance due to more gm and provides 16.3%,48.4%more gain than SLC and DLSC,respectively and it also provides better linearity.All the results are obtained using the VisualTCAD tool.
基金This work was supported by The National Natural Science Foundation of China(No.61402537)Sichuan Science and Technology Program(Nos.2019ZDZX0006,2020YFQ0056)+1 种基金the West Light Foundation of Chinese Academy of Sciences(201899)the Talents by Sichuan provincial Party Committee Organization Department,and Science and Technology Service Network Initiative(KFJ-STS-QYZD-2021-21-001).
文摘At present,deep learning has been well applied in many fields.However,due to the high complexity of hypothesis space,numerous training samples are usually required to ensure the reliability of minimizing experience risk.Therefore,training a classifier with a small number of training examples is a challenging task.From a biological point of view,based on the assumption that rich prior knowledge and analogical association should enable human beings to quickly distinguish novel things from a few or even one example,we proposed a dynamic analogical association algorithm to make the model use only a few labeled samples for classification.To be specific,the algorithm search for knowledge structures similar to existing tasks in prior knowledge based on manifold matching,and combine sampling distributions to generate offsets instead of two sample points,thereby ensuring high confidence and significant contribution to the classification.The comparative results on two common benchmark datasets substantiate the superiority of the proposed method compared to existing data generation approaches for few-shot learning,and the effectiveness of the algorithm has been proved through ablation experiments.
文摘With the continuous development of science and technology, digital signal processing is more and more widely used in various fields. Among them, the analog-to-digital converter (ADC) is one of the key components to convert analog signals to digital signals. As a common type of ADC, 12-bit sequential approximation analog-to-digital converter (SAR ADC) has attracted extensive attention for its performance and application. This paper aims to conduct in-depth research and analysis of 12-bit SAR ADC to meet the growing demands of digital signal processing. This article designs a 12-bit, successive approximation analog-to-digital converter (SAR ADC) with a sampling rate of 5 MS/s. The overall circuit adopts a fully differential structure, with key modules including DAC capacitor array, comparator, and control logic. According to the DAC circuit in this paper, a fully differential capacitor DAC array structure is proposed to reduce the area of layout DAC. The comparator uses a digital dynamic comparator to improve the ADC conversion speed. The chip is designed based on the SMIC180 nm CMOS process. The simulation results show that when the sampling rate is 5 MS/s, the effective bit of SAR ADC is 11.92 bit, the SNR is 74.62 dB, and the SFDR is 89.24 dB.
基金financially supported by the National Basic Research Program of China (Grant No. 2009CB421 401)
文摘The authors use numerical model integral products in a third level forecast of synthetically multi-level analog forecast technology.This is one of the strongest points of this study,which also includes the re-ducing mean vacant-forecast rate method,which pos-sesses many advantages with regard to filtering the analog term.Moreover,the similitude degree between samples is assessed using a combination of meteorological elements,which works better than that described using a single element in earlier analog forecast studies.Based on these techniques,the authors apply the model output,air sounding,surface observation and weather map data from 1990 to 2002 to perform an analog experiment of the quasi-stationary front rainstorm.The most important re-sults are as follows:(1) The forecast successful index is 0.36,and was improved after the forecast model was re-vised.(2) The forecast precise rate (0.59) and the lost-forecast rate (0.33) are also better than those of other methods.(3) Based on the model output data,the syn-thetically multilevel analog forecast technology can pro-duce more accurate forecasts of a quasi-stationary front rainstorm.(4) Optimal analog elements reveal that trig-gering mechanisms are located in the lower troposphere while upper level systems are more important in main-taining the phase of the rainstorm.These variables should be first taken into account in operational forecasts of the quasi-stationary front rainstorm.(5) In addition,experi-ments reveal that the position of the key zone is mainly decided by the position of the system causing the heavy rainfall.
基金Supported by the CAS/SAFEA International Partnership Program for Creative Research Teams,National High Technology Research and Develop Program of China(2012AA012301)National Science and Technology Major Project of China(2013ZX03006004)
文摘The drive towards shorter design cycles for analog integrated circuits has given impetus to the development of Field Programmable Analog Arrays(FPAAs),which are the analogue counterparts of Field Programmable Gate Arrays(FPGAs).In this paper,we present a new design methodology which using FPAA as a powerful analog front-end processing platform in the smart sensory microsystem.The proposed FPAA contains 16 homogeneous mixed-grained Configurable Analog Blocks(CABs) which house a variety of processing elements especially the proposed fine-grained Core Configurable Amplifiers(CCAs).The high flexible CABs allow the FPAA operating in both continuous-time and discrete-time approaches suitable to support variety of sensors.To reduce the nonideal parasitic effects and save area,the fat-tree interconnection network is adopted in this FPAA.The functionality of this FPAA is demonstrated through embedding of voltage and capacitive sensor signal readout circuits and a configurable band pass filter.The minimal detectable voltage and capacitor achieves 38 uV and 8.3 aF respectively within 100 Hz sensor bandwidth.The power consumption comparison of CCA in three applications shows that the FPAA has high power efficiency.And the simulation results also show that the FPAA has good tolerance with wide PVT variations.
基金Supported by the National Natural Science Foundation of China(61433003,61273150)Beijing Higher Education Young Elite Teacher Project
文摘A micro-extended-analog-computer(uEAC)is developed on the basis of Rubel's extended analog computer(EAC)model.Through the uEAC mathematical model,the resistance properties of the conductive sheet,several feedback uEAC models,and a more flexible uEAC cell structure with a multilevel hierarchy are discussed.Futhermore,for the dynamic uEAC array with a linear Lukasiewicz function,a nonlinear differential equation description is presented,and then a sufficient global asymptotic stability condition is derived by utilizing a Lyapunov function and a Lipchitz function.Finally,comparative simulations for a cam servo mechanism system are conducted to verify the capability of the uEAC array as an adaptive controller.
文摘As a method of logical thinking,analogical inference has a long history both in ancient Greece and in the ancient East,and has been widely used in the daily life.Even today it still plays an important role in understanding and improving the world.Particularly,its cognitive function is not only reflected in the interpretation and further understanding of the existing knowledge,but more importantly,it can still improve our scientific level,expand our cognitive field,and help us open up the unknown field.That,of course,is where its innovation lies.From the perspective of analogical inference,its innovative function should be based on the identical or at least the similar relationship between the things.In addition,it should also be based on the ability of imagination played by the cognition subject.
文摘We considered the physiological mechanisms of functioning of the retina’s neural network. It is marked that the primary function of a neural network is an analog-to-digital conversion of the receptor potential of photoreceptor into the pulse-to-digital signal to ganglion cells. We showed the role of different types of neurons in the work of analog-to-digital converter. We gave the equivalent circuit of this converter. We researched the mechanism of the numeric coding of the receptor potential of the photoreceptor.
文摘New voltage-controlled floating inductors employing CFOAs and an analog multiplier have been presented which have the attractive features of using a canonic number of passive components (only two resistors and a capacitor) and not requiring any component-matching conditions and design constraints for the intended type of inductance realization. The workability and applications of the new circuits have been demonstrated by SPICE simulation and hardware experimental results based upon AD844-type CFOAs and AD633-type/MPY534 type analog multipliers.
文摘This paper proposes novel floating-gate MOSFET (FGMOS) based Voltage Buffer, Analog Inverter and Winner-Take-All (WTA) circuits. The proposed circuits have low power dissipation. All proposed circuits are simulated using SPICE in 180 nm CMOS technology with supply voltages of ±1.25 V. The simulation results demonstrate increase in input range for FGMOS based voltage buffer and analog inverter and maximum power dissipation of 0.5 mW, 1.9 mW and 0.429 mW for FGMOS based voltage buffer, analog inverter and WTA circuits, respectively. The proposed circuits are intended to find applications in low voltage, low power consumer electronics.
基金the National Natural Science Foundation of China,No.31500650。
文摘BACKGROUND Nucleos(t)ide analog(NA)has shown limited effectiveness against hepatitis B surface antigen(HBsAg)clearance in chronic hepatitis B(CHB)patients.AIM To evaluate the efficacy and safety of add-on peginterferonα-2a(peg-IFNα-2a)to an ongoing NA regimen in CHB patients.METHODS In this observational study,195 CHB patients with HBsAg≤1500 IU/m L,hepatitis B e antigen(HBeAg)-negative(including HBeAg-negative patients or HBeAg-positive patients who achieved HBeAg-negative after antiviral treatment with NA)and hepatitis B virus-deoxyribonucleic acid<1.0×10^2 IU/mL after over 1 year of NA therapy were enrolled between November 2015 and December2018 at the Second Affiliated Hospital of Xi'an Jiaotong University,China.Patients were given the choice between receiving either peg-IFNα-2a add-on therapy to an ongoing NA regimen(add-on group,n=91)or continuous NA monotherapy(monotherapy group,n=104)after being informed of the benefits and risks of the peg-IFNα-2a therapy.Total therapy duration of peg-IFNα-2a was 48 wk.All patients were followed-up to week 72(24 wk after discontinuation of peg-IFNα-2a).The primary endpoint was the proportion of patients with HBsAg clearance at week 72.RESULTS Demographic and baseline characteristics were comparable between the two groups.Intention-to-treatment analysis showed that the HBsAg clearance rate in the add-on group and monotherapy group was 37.4%(34/91)and 1.9%(2/104)at week 72,respectively.The HBsAg seroconversion rate in the add-on group was 29.7%(27/91)at week 72,and no patient in the monotherapy group achieved HBsAg seroconversion at week 72.The HBsAg clearance and seroconversion rates in the add-on group were significantly higher than in the monotherapy group at week 72(P<0.001).Younger patients,lower baseline HBsAg concentration,lower HBsAg concentrations at weeks 12 and 24,greater HBsAg decline from baseline to weeks 12 and 24 and the alanine aminotransferase≥2×upper limit of normal during the first 12 wk of therapy were strong predictors of HBsAg clearance in patients with peg-IFNα-2a add-on treatment.Regarding the safety of the treatment,4.4%(4/91)of patients in the add-on group discontinued peg-IFNα-2a due to adverse events.No severe adverse events were noted.CONCLUSION Peg-IFNα-2a as an add-on therapy augments HBsAg clearance in HBeAg-negative CHB patients with HBsAg≤1500 IU/m L after over 1 year of NA therapy.
