期刊文献+
共找到11篇文章
< 1 >
每页显示 20 50 100
A Slice Analysis-Based Bayesian Inference Dynamic Power Model for CMOS Combinational Circuits
1
作者 陈杰 佟冬 +2 位作者 李险峰 谢劲松 程旭 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2008年第3期502-509,共8页
To improve the accuracy and speed in cycle-accurate power estimation, this paper uses multiple dimensional coefficients to build a Bayesian inference dynamic power model. By analyzing the power distribution and intern... To improve the accuracy and speed in cycle-accurate power estimation, this paper uses multiple dimensional coefficients to build a Bayesian inference dynamic power model. By analyzing the power distribution and internal node state, we find the deficiency of only using port information. Then, we define the gate level number computing method and the concept of slice, and propose using slice analysis to distill switching density as coefficients in a special circuit stage and participate in Bayesian inference with port information. Experiments show that this method can reduce the power-per-cycle estimation error by 21.9% and the root mean square error by 25.0% compared with the original model, and maintain a 700 + speedup compared with the existing gate-level power analysis technique. 展开更多
关键词 slice analysis Bayesian inference power model CMOS combinational circuit
下载PDF
A new approach to test generation for combinational circuits
2
作者 赵春晖 侯艳丽 +1 位作者 胡佳伟 兰海燕 《Journal of Harbin Institute of Technology(New Series)》 EI CAS 2009年第1期61-65,共5页
Aimed at the generation of high-quality test set in the shortest possible time, the test generation for combinational circuits (CC) based on the chaotic particle swarm optimization (CPSO) algorithm is presented ac... Aimed at the generation of high-quality test set in the shortest possible time, the test generation for combinational circuits (CC) based on the chaotic particle swarm optimization (CPSO) algorithm is presented according to the analysis of existent problems of CC test generation, and an appropriate CPSO algorithm model has been constructed. With the help of fault simulator, the test set of ISCAS' 85 benchmark CC is generated using the CPSO, and some techniques are introduced such as half-random generation, and simulation of undetected fauhs.with original test vector, and inverse test vector. Experimental results show that this algorithm can generate the same fault coverage and small-size test set in short time compared with other known similar methods, which proves that the proposed method is applicable and effective. 展开更多
关键词 test generation combinational circuits particle swarm ootimization: chaotic ontimization
下载PDF
Pseudo-Random Test Generation for Large Combinational Circuits
3
作者 李忠诚 闵应骅 《Journal of Computer Science & Technology》 SCIE EI CSCD 1992年第1期19-28,共10页
In this paper,a simulation system of pseudo-random testing is described first to investigate the characteristics of pseudo-random testing.Several interesting experimental results are obtained.It is found out that init... In this paper,a simulation system of pseudo-random testing is described first to investigate the characteristics of pseudo-random testing.Several interesting experimental results are obtained.It is found out that initial states of pseudo-random sequences have little effect on fault coverage.Fixed connection between LFSR outputs and circuit inputs in which the number of LFSR stages m is less than the number of circuit inputs n leads to low fault coverage,and the fault coverage is reduced as m decreases.The local unrandomness of pseudo-random sequences is exposed clearly.Generally,when an LFSR is employed as a pseudo-random generator,there are at least as many LFSR stages as circuit inputs.However,for large circuits under test with hundreds of inputs,there are drawbacks of using an LFSR with hundreds of stages.In the paper,a new design for a pseudo-random pattern generator is proposed in which m<n.The relationship between test length and the number of LFSR stages is discussed in order to obtain necessary,fault coverage.It is shown that the design cannot only save LFSR hardware but also reduce test length without loss of fault coverage,and is easy to implement. The experimental results are provided for the 10 Benchmark Circuits to show the effectiveness of the generator. 展开更多
关键词 LFSR Pseudo-Random Test Generation for Large combinational circuits LENGTH TEST
原文传递
Parallel Critical Path Tracing——A Fault Simulation Algorithm for Combinational Circuits
4
作者 魏道政 《Journal of Computer Science & Technology》 SCIE EI CSCD 1990年第2期156-163,共8页
Critical path tracing,a fault simulation method for gate-level combinational circuits,is extended to theparallel critical path tracing for functional block-level combinational circuits.If the word length of the hostco... Critical path tracing,a fault simulation method for gate-level combinational circuits,is extended to theparallel critical path tracing for functional block-level combinational circuits.If the word length of the hostcomputer is m,then the parallel critical path tracing will be approximately m times faster than the originalone. 展开更多
关键词 A Fault Simulation Algorithm for combinational circuits Parallel Critical Path Tracing PATH SIMULATION
原文传递
A Complete Critical Path Algorithm for Test Generation of Combinational Circuits
5
作者 周权 魏道政 《Journal of Computer Science & Technology》 SCIE EI CSCD 1991年第1期74-82,共9页
It is known that critical path test generation method is not a complete algorithm for combinational circuits with reconvergent-fanout.In order to make it a complete algorithm,we put forward a reconvergent-fanout- orie... It is known that critical path test generation method is not a complete algorithm for combinational circuits with reconvergent-fanout.In order to make it a complete algorithm,we put forward a reconvergent-fanout- oriented technique,the principal critical path algorithm,propagating the critical value back to primary inputs along a single path,the principal critical path,and allowing multiple path sensitization if needed.Relationship among test patterns is also discussed to accelerate test generation. 展开更多
关键词 PATH A Complete Critical Path Algorithm for Test Generation of combinational circuits TEST
原文传递
Research of the test generation algorithm based on search state dominance for combinational circuit
6
作者 吴丽华 俞红娟 +1 位作者 王轸 马怀俭 《Journal of Harbin Institute of Technology(New Series)》 EI CAS 2006年第1期62-64,共3页
On the basis of EST (Equivalent STate hashing) algorithm, this paper researches a kind of test generation algorithm based on search state dominance for combinational circuit. According to the dominance relation of the... On the basis of EST (Equivalent STate hashing) algorithm, this paper researches a kind of test generation algorithm based on search state dominance for combinational circuit. According to the dominance relation of the E-frontier (evaluation frontier), we can prove that this algorithm can terminate unnecessary searching step of test pattern earlier than the EST algorithm through some examples, so this algorithm can reduce the time of test generation. The test patterns calculated can detect faults given through simulation. 展开更多
关键词 E-frontier test generation combinational circuit
下载PDF
The structure-based multi-fault test generation algorithm for combinational circuit
7
作者 商庆华 吴丽华 项傅佳 《Journal of Harbin Institute of Technology(New Series)》 EI CAS 2006年第4期452-454,共3页
In this paper the structure-based test generation algorithm has been studied for the problem that test patterns are obtained by determined finite faults set in the past. This Algorithm can find out all test patterns o... In this paper the structure-based test generation algorithm has been studied for the problem that test patterns are obtained by determined finite faults set in the past. This Algorithm can find out all test patterns one tithe, so faults detection is very convenient. By simulation, the smallest test patterns set can be obtained and faults coverage rate is 100%. 展开更多
关键词 combinational circuit test generation the smallest test patterns set
下载PDF
Circuit Compression Based on Similarity for RTL ATPG
8
作者 Ji Chen Jishun Kuang Dafang Zhang 《湖南大学学报(自然科学版)》 EI CAS CSCD 2000年第S2期78-85,共8页
This paper analyzes structural characteristics of signal vectors in combinational circuits with RTL description. Then, this paper presents the concept of the Basic Similar Circuit (BSC), a circuit constructed by compr... This paper analyzes structural characteristics of signal vectors in combinational circuits with RTL description. Then, this paper presents the concept of the Basic Similar Circuit (BSC), a circuit constructed by compressing the bit-width of vectored vectors in the original circuit. BSC shrinks the scale of the original circuit, thus improving the ATPG efficiency. Test patterns are derived from adjustment and assembling of precomputed sub-circuit test sets. Based on the deterministic algorithm, the ATPG method presented in this paper combines deterministic algorithms and undetermined methods. 展开更多
关键词 RTL combinational circuit similar circuit BSC VECTOR similar mapping ATPG
下载PDF
A weighted averaging method for signal probability of logic circuit combined with reconvergent fan-out structures
9
作者 Xiao Jie Ma Weifeng +1 位作者 William Lee Shi Zhanhui 《Journal of Southeast University(English Edition)》 EI CAS 2018年第2期173-181,共9页
By analyzing the structures of circuits,a novel approach for signal probability estimation of very large-scale integration(VLSI)based on the improved weighted averaging algorithm(IWAA)is proposed.Considering the failu... By analyzing the structures of circuits,a novel approach for signal probability estimation of very large-scale integration(VLSI)based on the improved weighted averaging algorithm(IWAA)is proposed.Considering the failure probability of the gate,first,the first reconvergent fan-ins corresponding to the reconvergent fan-outs were identified to locate the important signal correlation nodes based on the principle of homologous signal convergence.Secondly,the reconvergent fan-in nodes of the multiple reconverging structure in the circuit were identified by the sensitization path to determine the interference sources to the signal probability calculation.Then,the weighted signal probability was calculated by combining the weighted average approach to correct the signal probability.Finally,the reconvergent fan-out was quantified by the mixed-calculation strategy of signal probability to reduce the impact of multiple reconvergent fan-outs on the accuracy.Simulation results on ISCAS85 benchmarks circuits show that the proposed method has approximate linear time-space consumption with the increase in the number of the gate,and its accuracy is 4.2%higher than that of the IWAA. 展开更多
关键词 improved weighted averaging algorithm signal probability estimation gate error rate combinational logic circuits
下载PDF
Test Vector Optimization Using Pocofan-Poframe Partitionin
10
作者 P.PattunnaRajam Reeba korah G.Maria Kalavathy 《Computers, Materials & Continua》 SCIE EI 2018年第3期251-268,共18页
This paper presents an automated POCOFAN-POFRAME algorithm thatpartitions large combinational digital VLSI circuits for pseudo exhaustive testing. In thispaper, a simulation framework and partitioning technique are pr... This paper presents an automated POCOFAN-POFRAME algorithm thatpartitions large combinational digital VLSI circuits for pseudo exhaustive testing. In thispaper, a simulation framework and partitioning technique are presented to guide VLSIcircuits to work under with fewer test vectors in order to reduce testing time and todevelop VLSI circuit designs. This framework utilizes two methods of partitioningPrimary Output Cone Fanout Partitioning (POCOFAN) and POFRAME partitioning todetermine number of test vectors in the circuit. The key role of partitioning is to identifyreconvergent fanout branch pairs and the optimal value of primary input node N andfanout F partitioning using I-PIFAN algorithm. The number of reconvergent fanout andits locations are critical for testing of VLSI circuits and design for testability. Hence, theirselection is crucial in order to optimize system performance and reliability. In the presentwork, the design constraints of the partitioned circuit considered for optimizationincludes critical path delay and test time. POCOFAN-POFRAME algorithm uses theparameters with optimal values of circuits maximum primary input cone size (N) andminimum fan-out value (F) to determine the number of test vectors, number of partitionsand its locations. The ISCAS’85 benchmark circuits have been successfully partitioned,the test results of C499 shows 45% reduction in the test vectors and the experimentalresults are compared with other partitioning methods, our algorithm makes fewer testvectors. 展开更多
关键词 Pseudo exhaustive testing POCOFAN (Primary Output Cone FanoutPartitioning) POFRAME partitioning combinational digital VLSI circuit testing criticalpath delay testing time design for testability
下载PDF
All-atomristor logic gates
11
作者 Shu Wang Zhican Zhou +7 位作者 Fengyou Yang Shengyao Chen Qiaoxuan Zhang Wenqi Xiong Yusong Qu Zhongchang Wang Cong Wang Qian Liu 《Nano Research》 SCIE EI CSCD 2023年第1期1688-1694,共7页
The atomristor(monolayer two-dimensional(2D)-material memristor)is competitive in high-speed logic computing due to its binary feature,lower energy consumption,faster switch response,and so on.Yet to date,all-atomrist... The atomristor(monolayer two-dimensional(2D)-material memristor)is competitive in high-speed logic computing due to its binary feature,lower energy consumption,faster switch response,and so on.Yet to date,all-atomristor logic gates used for logic computing have not been reported due to the poor consistency of different atomristors in performance.Here,by studying band structures and electron transport properties of MoS2 atomristor,a comprehensive memristive mechanism is obtained.Guided by the simulation results,monolayer MoS2 with moderated defect concentration has been fabricated in the experiment,which can build atomristors with high performance and good consistency.Based on this,for the first time,MoS2 all-atomristor logic gates are realized successfully.As a demonstration,a half-adder based on the logic gates and a binary neural network(BNN)based on crossbar arrays are evaluated,indicating the applicability in various logic computing circumstances.Owing to shorter transition time and lower energy consumption,all-atomristor logic gates will open many new opportunities for next-generation logic computing and data processing. 展开更多
关键词 atomristor logic gates combinational logic circuit neural network defect concentration
原文传递
上一页 1 下一页 到第
使用帮助 返回顶部