The Gauss-Seidel method is effective to solve the traditional sparse linear system. In the paper, we define a class of sparse linear systems in iterative algorithm. The iterative method for linear system can be extend...The Gauss-Seidel method is effective to solve the traditional sparse linear system. In the paper, we define a class of sparse linear systems in iterative algorithm. The iterative method for linear system can be extended to the dummy sparse linear system. We apply the Gauss-Seidel method, which is one of the iterative methods for linear system, to the thermal model of floorplan of VLSI physical design. The experimental results of dummy sparse linear system are computed by using Gauss-Seidel method that have shown our theory analysis and extendibility. The iterative time of our incremental thermal model is 5 times faster than that of the inverting matrix method.展开更多
Floorplanning is a prominent area in the Very Large-Scale Integrated (VLSI) circuit design automation, because it influences the performance, size, yield and reliability of the VLSI chips. It is the process of estimat...Floorplanning is a prominent area in the Very Large-Scale Integrated (VLSI) circuit design automation, because it influences the performance, size, yield and reliability of the VLSI chips. It is the process of estimating the positions and shapes of the modules. A high packing density, small feature size and high clock frequency make the Integrated Circuit (IC) to dissipate large amount of heat. So, in this paper, a methodology is presented to distribute the temperature of the module on the layout while simultaneously optimizing the total area and wirelength by using a hybrid Particle Swarm Optimization-Harmony Search (HPSOHS) algorithm. This hybrid algorithm employs diversification technique (PSO) to obtain global optima and intensification strategy (HS) to achieve the best solution at the local level and Modified Corner List algorithm (MCL) for floorplan representation. A thermal modelling tool called hotspot tool is integrated with the proposed algorithm to obtain the temperature at the block level. The proposed algorithm is illustrated using Microelectronics Centre of North Carolina (MCNC) benchmark circuits. The results obtained are compared with the solutions derived from other stochastic algorithms and the proposed algorithm provides better solution.展开更多
Outline-free floorplanning focuses on area and wirelength reductions, which are usually meaningless, since they can hardly satisfy modern design requirements. We concentrate on a more difficult and useful issue, fixed...Outline-free floorplanning focuses on area and wirelength reductions, which are usually meaningless, since they can hardly satisfy modern design requirements. We concentrate on a more difficult and useful issue, fixed-outline floorplanning. This issue imposes fixed-outline constraints on the outline-free floorplanning, making the physical design more interesting and challenging. The contributions of this paper are primarily twofold. First, a modified simulated annealing(MSA) algorithm is proposed. In the beginning of the evolutionary process, a new attenuation formula is used to decrease the temperature slowly, to enhance MSA's global searching capacity. After a period of time, the traditional attenuation formula is employed to decrease the temperature rapidly, to maintain MSA's local searching capacity. Second, an excessive area model is designed to guide MSA to find feasible solutions readily. This can save much time for refining feasible solutions. Additionally, B*-tree representation is known as a very useful method for characterizing floorplanning. Therefore, it is employed to perform a perturbing operation for MSA. Finally, six groups of benchmark instances with different dead spaces and aspect ratios—circuits n10, n30, n50, n100, n200, and n300—are chosen to demonstrate the efficiency of our proposed method on fixed-outline floorplanning. Compared to several existing methods, the proposed method is more efficient in obtaining desirable objective function values associated with the chip area, wirelength, and fixed-outline constraints.展开更多
This paper studies the buffer planning problem for interconnect-centric floorplanning for nanometer technologies. The dead-spaces are the spaces left unused within a placement that are not held by any circuit block. I...This paper studies the buffer planning problem for interconnect-centric floorplanning for nanometer technologies. The dead-spaces are the spaces left unused within a placement that are not held by any circuit block. In this paper, we proposed a buffer planning algorithm based on dead space redistribution to make good use of dead-spaces for buffer insertion. Associated with circuit blocks under topological representations, the dead space can be redistributed by moving freely some circuit blocks within their rooms in the placement. The total area and the topology of the placement keep unchanged while doing the dead space redistribution. The number of nets satisfying the delay constraint can be increased by redistributing the dead space all over the placement, which has been demonstrated by the experimental results. The increment of the number of nets that meet delay constraint is 9% on an average.展开更多
We present a novel incremental algorithm for non-slicing floorplans based on the corner block list representation. The horizontal and vertical adjacency graphs are derived from the packing of the initial floorplanning...We present a novel incremental algorithm for non-slicing floorplans based on the corner block list representation. The horizontal and vertical adjacency graphs are derived from the packing of the initial floorplanning results. Based on the critical path and the accumulated slack distances we define,we choose the best position for insertion and do a series of operations incrementally, such as deleting modules, adding modules, and resizing modules quickly. This incremental floorplanning algorithm has a very high speed less than 1μm,which is one of the most important measures in this research. The algorithm preserves the original good performances on area and wire length. It can also supply other tools with good physical estimates for area, wire length, and other performance guidelines.展开更多
We present a deterministic algorithm for large-scale VLSI module placement. Following the less flexibility first （LFF） principle,we simulate a manual packing process in which the concept of placement by stages is in...We present a deterministic algorithm for large-scale VLSI module placement. Following the less flexibility first （LFF） principle,we simulate a manual packing process in which the concept of placement by stages is introduced to reduce the overall evaluation complexity. The complexity of the proposed algorithm is （N1 ＋ N2 ） × O（ n^2 ） ＋ N3× O（n^4lgn） ,where N1, N2 ,and N3 denote the number of modules in each stage, N1 ＋ N2 ＋ N3 = n, and N3〈〈 n. This complexity is much less than the original time complexity of O（n^5lgn）. Experimental results indicate that this approach is quite promising.展开更多
Floorplan, clock network and power plan are crucial steps in deep sub-micron system-on-chip design. A novel di- agonal floorplan is integrated to enhance the data sharing between different cores in system-on-chip. Cus...Floorplan, clock network and power plan are crucial steps in deep sub-micron system-on-chip design. A novel di- agonal floorplan is integrated to enhance the data sharing between different cores in system-on-chip. Custom clock network con- taining hand-adjusted buffers and variable routing rules is constructed to realize balanced synchronization. Effective power plan considering both IR drop and electromigration achieves high utilization and maintains power integrity in our MediaSoC. Using such methods, deep sub-micron design challenges are managed under a fast prototyping methodology, which greatly shortens the design cycle.展开更多
With the rapid development of deep submicron (DSM) VLSI circuit designs, many issues such as time closure and power consumption are making the physical designs more and more challenging. In this review paper we provid...With the rapid development of deep submicron (DSM) VLSI circuit designs, many issues such as time closure and power consumption are making the physical designs more and more challenging. In this review paper we provide readers with some recent progress of the VLSI physical designs. The recent developments of floorplanning and placement, interconnect effects, modeling and delay, buffer insertion and wire sizing, circuit order reduction, power grid analysis, parasitic extraction, and clock signal distribution are briefly reviewed.展开更多
Automated floorplanning or space layout planning has been a long-standing NP-hard problem in the field of computer-aided design,with applications in integrated circuits,architecture,urbanism,and operational research.I...Automated floorplanning or space layout planning has been a long-standing NP-hard problem in the field of computer-aided design,with applications in integrated circuits,architecture,urbanism,and operational research.In this paper,we introduce GenFloor,an interactive design system that takes geometrical,topological,and performance goals and constraints as input and provides optimized spatial design solutions as output.As part of our work,we propose three novel permutation methods for existing space layout graph representations,namely O-Tree and B*-Tree representations.We implement our proposed floorplanning methods as a package for Dynamo,a visual programming tool,with a custom GUI and additional evaluation functionalities to facilitate designers in their generative design workflow.Furthermore,we illustrate the performance of GenFloor in two sets of case-study experiments for residential floorplanning tasks by(a)measuring the ability of the proposed system to find a known optimal solution,and(b)observing how the system can generate diverse floorplans while addressing given a constant residential design problem.Our results indicate that convergence to the global optimum is achieved while offering a diverse set of solutions of a residential floorplan corresponding to local optimums of the solution landscape.展开更多
With the recent advent of deep submicron technology and new packing schemes, the components in the integrated circuit are often not rectangular. On the basis of the representation of Corner Block List （CBL）, we prop...With the recent advent of deep submicron technology and new packing schemes, the components in the integrated circuit are often not rectangular. On the basis of the representation of Corner Block List （CBL）, we propose a new method of handling rectilinear blocks. In this paper, the handling of the rectilinear blocks is simplified by transforming the L/T- shaped block problem into the Mign-abutment constraint problem. We devise the block rejoining process and block alignment operation for forming the L/T-shaped blocks into their original configurations. The shape flexibility of the soft blocks, and the rotation and reflection of L/T-shaped blocks are exploited to obtain a tight packing. The empty rooms are introduced to the process of block rejoining. The efficiency and effectiveness of the proposed method are demonstrated by the experimental results on a set of some benchmark examples.展开更多
Floorplanning is a critical phase in physical design of VLSI circuits. The stochastic optimization method is widely used to handle this NP-hard problem. The key to the floorplanning algorithm based on stochastic optim...Floorplanning is a critical phase in physical design of VLSI circuits. The stochastic optimization method is widely used to handle this NP-hard problem. The key to the floorplanning algorithm based on stochastic optimization is to encode the floorplan structure properly. In this paper, corner block list (CBL)-a new efficient topological representation for non-slicing floorplan-is proposed with applications to VLSI floorplan. Given a corner block list, it takes only linear time to construct the floorplan. In floorplanning of typical VLSI design, some blocks are required to satisfy some constraints in the final packing. Boundary constraint is one kind of those constraints to pack some blocks along the pre-specified boundaries of the final chip so that the blocks are easier to be connected to certain I/O pads. We implement the boundary constraint algorithm for general floorplan by extending CBL. Our contribution is to find the necessary and sufficient characterization of the blocks along the boundary represented by CBL. We can check the boundary constraints by scanning the intermediate solutions in linear time during the simulated annealing process and fix the corner block list in case the constraints are violated. The experiment results are demonstrated by several examples of MCNC benchmarks and the performance is remarkable.展开更多
As the feature size of integrated circuits is reduced to the deep sub-micron level or the nanometer level, the interconnect delay is becoming more and more important in determining the total delay of a circuit. Re-syn...As the feature size of integrated circuits is reduced to the deep sub-micron level or the nanometer level, the interconnect delay is becoming more and more important in determining the total delay of a circuit. Re-synthesis after floorplan is expected to be very helpful for reducing the interconnect delay of a circuit. In this paper, a force-balance-based re-synthesis algorithm for interconnect delay optimization after floorplan is proposed. The algorithm optimizes the interconnect delay by changing the operation scheduling and the functional unit allocation and binding. With this method the number and positions of all functional units are not changed, but some operations are allocated or bound to different units. Preliminary experimental results show that the interconnect wire delays are reduced efficiently without destroying the floorplan performance.展开更多
Bounded Slice-line Grid (BSG) is an elegant representation of block placement, because it is very intuitionistic and has the advantage of handling various placement constraints. However, BSG has attracted little atten...Bounded Slice-line Grid (BSG) is an elegant representation of block placement, because it is very intuitionistic and has the advantage of handling various placement constraints. However, BSG has attracted little attention because its evaluation is very time-consuming. This paper proposes a simple algorithm independent of the BSG size to evaluate the BSG representation in O(n log log n) time, where n is the number of blocks. In the algorithm, the BSG-rooms are assigned with integral coordinates firstly, and then a linear sorting algorithm is applied on the BSG-rooms where blocks are assigned to compute two block sequences, from which the block placement can be obtained in O(n log log n) time. As a consequence, the evaluation of the BSG is completed in O(n log log n) time, where n is the number of blocks. The proposed algorithm is much faster than the previous graph-based O(n(2)) algorithm. The experimental results demonstrate the efficiency of the algorithm.展开更多
This paper aims to contribute to the development of spatial criteria for adaptive capacity,which is identified as one important factor for the transition towards more circular housing design.The paper focuses on the k...This paper aims to contribute to the development of spatial criteria for adaptive capacity,which is identified as one important factor for the transition towards more circular housing design.The paper focuses on the kitchen,as an important function of the home which is connected to large resource flows and is exposed to frequent renovations and replacements.This paper identifies spatial characteristics of the kitchen and evaluates their potential to accommodate circular solutions focusing on adaptive capacity.As a first step,previous literature on the spatial characteristics of kitchens and indicators that support adaptability is reviewed.These are then used to develop an analytical framework to assess the adaptive capacity and circularity potential of 3624 kitchens in contemporary Swedish apartments.A qualitative approach in combination with quantitative methods is employed to analyse the selected sample.The main contributions of this paper include its spatial analytical framework,its descriptive presentation of contemporary kitchen and apartment designs,and its adaptive capacity assessment of the studied kitchens.The results point out that although the overcapacity of the floor area of kitchens and apartments can have significance for adaptability,it is not the only determinative spatial characteristics.The windows’location and distribution,the number of door openings and traffic zones,the shafts’location and accessibility from multiple rooms,the room typology and the kitchen typology can improve the adaptive capacity and circularity potential of kitchens and dwellings.The findings show that in contemporary floorplans advantageous design solutions connected to the identified spatial characteristics are not applied in a systematic way.Further research is necessary to define the exact measures of the individual spatial characteristics and their combined application in multiresidential floorplan design.展开更多
文摘The Gauss-Seidel method is effective to solve the traditional sparse linear system. In the paper, we define a class of sparse linear systems in iterative algorithm. The iterative method for linear system can be extended to the dummy sparse linear system. We apply the Gauss-Seidel method, which is one of the iterative methods for linear system, to the thermal model of floorplan of VLSI physical design. The experimental results of dummy sparse linear system are computed by using Gauss-Seidel method that have shown our theory analysis and extendibility. The iterative time of our incremental thermal model is 5 times faster than that of the inverting matrix method.
文摘Floorplanning is a prominent area in the Very Large-Scale Integrated (VLSI) circuit design automation, because it influences the performance, size, yield and reliability of the VLSI chips. It is the process of estimating the positions and shapes of the modules. A high packing density, small feature size and high clock frequency make the Integrated Circuit (IC) to dissipate large amount of heat. So, in this paper, a methodology is presented to distribute the temperature of the module on the layout while simultaneously optimizing the total area and wirelength by using a hybrid Particle Swarm Optimization-Harmony Search (HPSOHS) algorithm. This hybrid algorithm employs diversification technique (PSO) to obtain global optima and intensification strategy (HS) to achieve the best solution at the local level and Modified Corner List algorithm (MCL) for floorplan representation. A thermal modelling tool called hotspot tool is integrated with the proposed algorithm to obtain the temperature at the block level. The proposed algorithm is illustrated using Microelectronics Centre of North Carolina (MCNC) benchmark circuits. The results obtained are compared with the solutions derived from other stochastic algorithms and the proposed algorithm provides better solution.
基金supported by the National Natural Science Foundation of China(Nos.61403174 and 61503165)the Natural Science Foundation of the Jiangsu Higher Education Institutions of China(No.14KJB 520011)the Jiangsu Provincial Science Foundation for Youths(No.BK20150239)
文摘Outline-free floorplanning focuses on area and wirelength reductions, which are usually meaningless, since they can hardly satisfy modern design requirements. We concentrate on a more difficult and useful issue, fixed-outline floorplanning. This issue imposes fixed-outline constraints on the outline-free floorplanning, making the physical design more interesting and challenging. The contributions of this paper are primarily twofold. First, a modified simulated annealing(MSA) algorithm is proposed. In the beginning of the evolutionary process, a new attenuation formula is used to decrease the temperature slowly, to enhance MSA's global searching capacity. After a period of time, the traditional attenuation formula is employed to decrease the temperature rapidly, to maintain MSA's local searching capacity. Second, an excessive area model is designed to guide MSA to find feasible solutions readily. This can save much time for refining feasible solutions. Additionally, B*-tree representation is known as a very useful method for characterizing floorplanning. Therefore, it is employed to perform a perturbing operation for MSA. Finally, six groups of benchmark instances with different dead spaces and aspect ratios—circuits n10, n30, n50, n100, n200, and n300—are chosen to demonstrate the efficiency of our proposed method on fixed-outline floorplanning. Compared to several existing methods, the proposed method is more efficient in obtaining desirable objective function values associated with the chip area, wirelength, and fixed-outline constraints.
文摘This paper studies the buffer planning problem for interconnect-centric floorplanning for nanometer technologies. The dead-spaces are the spaces left unused within a placement that are not held by any circuit block. In this paper, we proposed a buffer planning algorithm based on dead space redistribution to make good use of dead-spaces for buffer insertion. Associated with circuit blocks under topological representations, the dead space can be redistributed by moving freely some circuit blocks within their rooms in the placement. The total area and the topology of the placement keep unchanged while doing the dead space redistribution. The number of nets satisfying the delay constraint can be increased by redistributing the dead space all over the placement, which has been demonstrated by the experimental results. The increment of the number of nets that meet delay constraint is 9% on an average.
文摘We present a novel incremental algorithm for non-slicing floorplans based on the corner block list representation. The horizontal and vertical adjacency graphs are derived from the packing of the initial floorplanning results. Based on the critical path and the accumulated slack distances we define,we choose the best position for insertion and do a series of operations incrementally, such as deleting modules, adding modules, and resizing modules quickly. This incremental floorplanning algorithm has a very high speed less than 1μm,which is one of the most important measures in this research. The algorithm preserves the original good performances on area and wire length. It can also supply other tools with good physical estimates for area, wire length, and other performance guidelines.
文摘We present a deterministic algorithm for large-scale VLSI module placement. Following the less flexibility first （LFF） principle,we simulate a manual packing process in which the concept of placement by stages is introduced to reduce the overall evaluation complexity. The complexity of the proposed algorithm is （N1 ＋ N2 ） × O（ n^2 ） ＋ N3× O（n^4lgn） ,where N1, N2 ,and N3 denote the number of modules in each stage, N1 ＋ N2 ＋ N3 = n, and N3〈〈 n. This complexity is much less than the original time complexity of O（n^5lgn）. Experimental results indicate that this approach is quite promising.
基金Project supported by the Hi-Tech Research and Development Pro-gram (863) of China (No. 2002AA1Z1140)the Fok Ying TongEducation Foundation (No. 94031), China
文摘Floorplan, clock network and power plan are crucial steps in deep sub-micron system-on-chip design. A novel di- agonal floorplan is integrated to enhance the data sharing between different cores in system-on-chip. Custom clock network con- taining hand-adjusted buffers and variable routing rules is constructed to realize balanced synchronization. Effective power plan considering both IR drop and electromigration achieves high utilization and maintains power integrity in our MediaSoC. Using such methods, deep sub-micron design challenges are managed under a fast prototyping methodology, which greatly shortens the design cycle.
文摘With the rapid development of deep submicron (DSM) VLSI circuit designs, many issues such as time closure and power consumption are making the physical designs more and more challenging. In this review paper we provide readers with some recent progress of the VLSI physical designs. The recent developments of floorplanning and placement, interconnect effects, modeling and delay, buffer insertion and wire sizing, circuit order reduction, power grid analysis, parasitic extraction, and clock signal distribution are briefly reviewed.
文摘Automated floorplanning or space layout planning has been a long-standing NP-hard problem in the field of computer-aided design,with applications in integrated circuits,architecture,urbanism,and operational research.In this paper,we introduce GenFloor,an interactive design system that takes geometrical,topological,and performance goals and constraints as input and provides optimized spatial design solutions as output.As part of our work,we propose three novel permutation methods for existing space layout graph representations,namely O-Tree and B*-Tree representations.We implement our proposed floorplanning methods as a package for Dynamo,a visual programming tool,with a custom GUI and additional evaluation functionalities to facilitate designers in their generative design workflow.Furthermore,we illustrate the performance of GenFloor in two sets of case-study experiments for residential floorplanning tasks by(a)measuring the ability of the proposed system to find a known optimal solution,and(b)observing how the system can generate diverse floorplans while addressing given a constant residential design problem.Our results indicate that convergence to the global optimum is achieved while offering a diverse set of solutions of a residential floorplan corresponding to local optimums of the solution landscape.
基金This work is supported by the National Natural Science Foundation of China （Grant Nos. 60473126 and 90407005）, National Natural Science Foundation of China and Hong Kong RGC Joint Project （Grant No. 60218004） and the Hi-Tech Research ＆ Development 863 Program of China （Grant Nos. 2004AA1Z1050 and 2002AA1Z1460）.
文摘With the recent advent of deep submicron technology and new packing schemes, the components in the integrated circuit are often not rectangular. On the basis of the representation of Corner Block List （CBL）, we propose a new method of handling rectilinear blocks. In this paper, the handling of the rectilinear blocks is simplified by transforming the L/T- shaped block problem into the Mign-abutment constraint problem. We devise the block rejoining process and block alignment operation for forming the L/T-shaped blocks into their original configurations. The shape flexibility of the soft blocks, and the rotation and reflection of L/T-shaped blocks are exploited to obtain a tight packing. The empty rooms are introduced to the process of block rejoining. The efficiency and effectiveness of the proposed method are demonstrated by the experimental results on a set of some benchmark examples.
文摘Floorplanning is a critical phase in physical design of VLSI circuits. The stochastic optimization method is widely used to handle this NP-hard problem. The key to the floorplanning algorithm based on stochastic optimization is to encode the floorplan structure properly. In this paper, corner block list (CBL)-a new efficient topological representation for non-slicing floorplan-is proposed with applications to VLSI floorplan. Given a corner block list, it takes only linear time to construct the floorplan. In floorplanning of typical VLSI design, some blocks are required to satisfy some constraints in the final packing. Boundary constraint is one kind of those constraints to pack some blocks along the pre-specified boundaries of the final chip so that the blocks are easier to be connected to certain I/O pads. We implement the boundary constraint algorithm for general floorplan by extending CBL. Our contribution is to find the necessary and sufficient characterization of the blocks along the boundary represented by CBL. We can check the boundary constraints by scanning the intermediate solutions in linear time during the simulated annealing process and fix the corner block list in case the constraints are violated. The experiment results are demonstrated by several examples of MCNC benchmarks and the performance is remarkable.
基金the National Natural Science Foundation of China (Nos. 90407005, 90207017, 60236020, and 60121120706)
文摘As the feature size of integrated circuits is reduced to the deep sub-micron level or the nanometer level, the interconnect delay is becoming more and more important in determining the total delay of a circuit. Re-synthesis after floorplan is expected to be very helpful for reducing the interconnect delay of a circuit. In this paper, a force-balance-based re-synthesis algorithm for interconnect delay optimization after floorplan is proposed. The algorithm optimizes the interconnect delay by changing the operation scheduling and the functional unit allocation and binding. With this method the number and positions of all functional units are not changed, but some operations are allocated or bound to different units. Preliminary experimental results show that the interconnect wire delays are reduced efficiently without destroying the floorplan performance.
文摘Bounded Slice-line Grid (BSG) is an elegant representation of block placement, because it is very intuitionistic and has the advantage of handling various placement constraints. However, BSG has attracted little attention because its evaluation is very time-consuming. This paper proposes a simple algorithm independent of the BSG size to evaluate the BSG representation in O(n log log n) time, where n is the number of blocks. In the algorithm, the BSG-rooms are assigned with integral coordinates firstly, and then a linear sorting algorithm is applied on the BSG-rooms where blocks are assigned to compute two block sequences, from which the block placement can be obtained in O(n log log n) time. As a consequence, the evaluation of the BSG is completed in O(n log log n) time, where n is the number of blocks. The proposed algorithm is much faster than the previous graph-based O(n(2)) algorithm. The experimental results demonstrate the efficiency of the algorithm.
基金The final revision of this paper was Garried out within the Gircular Kitchen 2.0 project founded by Vastra Gotalandsregionen(project number:20232029)and Formas-A Swedish Research Council for Sustainable Development(project number:202102454).
文摘This paper aims to contribute to the development of spatial criteria for adaptive capacity,which is identified as one important factor for the transition towards more circular housing design.The paper focuses on the kitchen,as an important function of the home which is connected to large resource flows and is exposed to frequent renovations and replacements.This paper identifies spatial characteristics of the kitchen and evaluates their potential to accommodate circular solutions focusing on adaptive capacity.As a first step,previous literature on the spatial characteristics of kitchens and indicators that support adaptability is reviewed.These are then used to develop an analytical framework to assess the adaptive capacity and circularity potential of 3624 kitchens in contemporary Swedish apartments.A qualitative approach in combination with quantitative methods is employed to analyse the selected sample.The main contributions of this paper include its spatial analytical framework,its descriptive presentation of contemporary kitchen and apartment designs,and its adaptive capacity assessment of the studied kitchens.The results point out that although the overcapacity of the floor area of kitchens and apartments can have significance for adaptability,it is not the only determinative spatial characteristics.The windows’location and distribution,the number of door openings and traffic zones,the shafts’location and accessibility from multiple rooms,the room typology and the kitchen typology can improve the adaptive capacity and circularity potential of kitchens and dwellings.The findings show that in contemporary floorplans advantageous design solutions connected to the identified spatial characteristics are not applied in a systematic way.Further research is necessary to define the exact measures of the individual spatial characteristics and their combined application in multiresidential floorplan design.
