Large scale digital beamforming(LS-DBFs)are widely used in satellite communications for spectrum reuse and transmission enhancement.SRAM-FPGAs are a popular option for software defined satellite platforms due to their...Large scale digital beamforming(LS-DBFs)are widely used in satellite communications for spectrum reuse and transmission enhancement.SRAM-FPGAs are a popular option for software defined satellite platforms due to their rich computation resources and high flexibility.However,they are sensitive to soft errors,which limit their application in space.This paper discusses the application of coding based fault tolerance schemes for the protection of LS-DBFs on software defined payloads.Since multiple FPGAs are usually needed to support the whole LS-DBFs system,different decomposition schemes are compared in terms of resource efficiency and reliability when the coding based scheme is applied to protect the DBFs on a FPGA.Theoretical analysis and hardware experiments shows that resource efficiency and reliability are a pair of contradictory requirements for decomposition schemes.The protection with vertical decomposition could improve the reliability by 96%with 1.5x redundancy.And the protection with horizontal decomposition could improve the reliability by 85%with 1.2 x redundancy.展开更多
For modern scaling devices,multiple cell upsets(MCUs)have become a major threat to high-reliability field-programmable gate array(FPGA)-based systems.Thus,both performing the worst-case irradiation tests to provide th...For modern scaling devices,multiple cell upsets(MCUs)have become a major threat to high-reliability field-programmable gate array(FPGA)-based systems.Thus,both performing the worst-case irradiation tests to provide the actual MCU response of devices and proposing an effective MCU distinction method are urgently needed.In this study,high-and medium-energy heavy-ion irradiations for the configuration random-access memory of 28 nm FPGAs are performed.An MCU extraction method supported by theoretical predictions is proposed to study the MCU sizes,shapes,and frequencies in detail.Based on the extraction method,the different percentages,and orientations of the large MCUs in both the azimuth and zenith directions determine the worse irradiation response of the FPGAs.The extracted largest 9-bit MCUs indicate that high-energy heavy ions can induce more severe failures than medium-energy ones.The results show that both the use of high-energy heavy ions during MCU evaluations and effective protection for the application of high-density 28 nm FPGAs in space are extremely necessary.展开更多
Field Programmable Gate Arrays(FPGAs)offer high capability in implementing of complex systems,and currently are an attractive solution for space system electronics.However,FPGAs are susceptible to radiation induced Si...Field Programmable Gate Arrays(FPGAs)offer high capability in implementing of complex systems,and currently are an attractive solution for space system electronics.However,FPGAs are susceptible to radiation induced Single-Event Upsets(SEUs).To insure reliable operation of FPGA based systems in a harsh radiation environment,various SEU mitigation techniques have been provided.In this paper we propose a system based on dynamic partial reconfiguration capability of the modern devices to evaluate the SEU fault effect in FPGA.The proposed approach combines the fault injection controller with the host FPGA,and therefore the hardware complexity is minimized.All of the SEU injection and evaluation requirements are performed by a soft-core which realized inside the host FPGA.Experimental results on some standard benchmark circuits reveal that the proposed system is able to speed up the fault injection campaign 50 times in compared to conventional method.展开更多
Multiple-bit upsets(MBUs)have become a threat to modern advanced field-programmable gate arrays(FPGAs)applications in radiation environments.Hence,many investigations have been conducted using mediumenergy heavy ions ...Multiple-bit upsets(MBUs)have become a threat to modern advanced field-programmable gate arrays(FPGAs)applications in radiation environments.Hence,many investigations have been conducted using mediumenergy heavy ions to study the effects of MBU radiation.However,high-energy heavy ions(HEHIs)greatly affect the size and percentage of MBUs because their ionizationtrack structures differ from those of medium-energy heavy ions.In this study,the different impacts of high-energy and medium-energy heavy ions on MBUs in 28 nm FPGAs as well as their mechanisms are thoroughly investigated.With the Geant4 calculation,more serious energy effects of HEHIs on MBU scales were successfully demonstrated.In addition,we identified worse MBU responses resulting from lowered voltages.The MBU orientation effect was observed in the radiation of different dimensions.The broadened ionization tracks for tilted tests in different dimensions could result in different MBU sizes.The results also revealed that the ionization tracks of tilted HEHIs have more severe impacts on the MBU scales than mediumenergy heavy ions with much higher linear energy transfer.Therefore,comprehensive radiation with HEHIs is indispensable for effective hardened designs to apply highdensity 28 nm FPGAs in deep space exploration.展开更多
With extensive use of flash-based field-programmable gate arrays(FPGAs) in military and aerospace applications, single-event effects(SEEs) of FPGAs induced by radiations have been a major concern. In this paper, we pr...With extensive use of flash-based field-programmable gate arrays(FPGAs) in military and aerospace applications, single-event effects(SEEs) of FPGAs induced by radiations have been a major concern. In this paper, we present SEE experimental study of a flash-based FPGA from Microsemi Pro ASIC3 product family. The relation between the cross section and different linear energy transfer(LET) values for the logic tiles and embedded RAM blocks is obtained. The results show that the sequential logic cross section depends not too much on operating frequency of the device. And the relationship between 0 →1 upsets(zeros) and 1 →0 upsets(ones) is different for different kinds of D-flip-flops. The devices are not sensitive to SEL up to a LET of 99.0 Me V cm2/mg.Post-beam tests show that the programming module is damaged due to the high-LET ions.展开更多
The characteristic of FPGA, motion estimation(ME) and the full search block matching arithmetic were introduced, it analyses the collectivity configuration of basic working flow in ME. Based on FPGA, the study concent...The characteristic of FPGA, motion estimation(ME) and the full search block matching arithmetic were introduced, it analyses the collectivity configuration of basic working flow in ME. Based on FPGA, the study concentrates on the control, computing and test part of ME chip implementation. In the end PCB of ME chip is designed and completed. ME is an important link of MPEG standard on picture compression, whose characteristics is its huge amount of data and computing task. So people often use special chip to meet the requirement, but there is still not such production in China at present.展开更多
Routing resources are the major bottlenecks in improving the performance and power consumption of the current FPGAs. Recently reported researches have shown that carbon nanotube field effect transistors(CNFETs) have c...Routing resources are the major bottlenecks in improving the performance and power consumption of the current FPGAs. Recently reported researches have shown that carbon nanotube field effect transistors(CNFETs) have considerable potentials for improving the delay and power consumption of the modern FPGAs. In this paper, hybrid CNFET-CMOS architecture is presented for FPGAs and then this architecture is evaluated to be used in modern FPGAs. In addition, we have designed and parameterized the CNFET-based FPGA switches and calibrated them for being utilized in FPGAs at 45 nm, 22 nm and 16 nm technology nodes.Simulation results show that the CNFET-based FPGA switches improve the current FPGAs in terms of performance, power consumption and immunity to process and temperature variations. Simulation results and analyses also demonstrate that the performance of the FPGAs is improved about 30%, on average and the average and leakage power consumptions are reduced more than 6% and 98% respectively when the CNFET switches are used instead of MOSFET FPGA switches. Moreover, this technique leads to more than 20.31%smaller area. It is worth mentioning that the advantages of CNFET-based FPGAs are more considerable when the size of FPGAs grows and also when the technology node becomes smaller.展开更多
An internal single event upset(SEU)mitigation technique is proposed,which reads back the configuration frames from the static random access memory(SRAM)-based field programmable gate array(FPGA)through an internal por...An internal single event upset(SEU)mitigation technique is proposed,which reads back the configuration frames from the static random access memory(SRAM)-based field programmable gate array(FPGA)through an internal port and compares them with those stored in the radiationhardened memory to detect and correct SEUs.Triple modular redundancy(TMR),which triplicates the circuit of the technique and uses majority voters to isolate any single upset within it,is used to enhance the reliability.Performance analysis shows that the proposed technique can satisfy the requirement of ordinary aerospace missions with less power dissipation,size and weight.The fault injection experiment validates that the proposed technique is capable of correcting most errors to protect spaceborne facilities from SEUs.展开更多
Power dissipation has become one of the key optimization conditions in logic design on field programmable gate arrays (FPGAs), thus the power estimation is necessary for logic design optimization. Nowadays, signal act...Power dissipation has become one of the key optimization conditions in logic design on field programmable gate arrays (FPGAs), thus the power estimation is necessary for logic design optimization. Nowadays, signal activity data created by logic simulation based on test vectors is essential to be used to determine the toggle rate of each signals and blocks in power estimation tools provided by field programmable gate array (FPGA) electronic design automation (EDA) tools. The accuracy of power estimation highly depends on the quality of test vectors, especially, pattern coverage. As probability distribution can describe the uncertainty signals, this work provides an algorithm which can estimate FPGAs power more effectively and accurately by using signal probability distribution rather than test vectors.展开更多
Field programmable gate array (FPGA) devices have become widespread in electronic systems due to their low design costs and reconfigurability.In battery-restricted applications such as handheld electronics systems,low...Field programmable gate array (FPGA) devices have become widespread in electronic systems due to their low design costs and reconfigurability.In battery-restricted applications such as handheld electronics systems,low-power FPGAs are in great demand.Leakage power almost equals dynamic power in modern integrated circuit technologies,so the reduction of leakage power leads to significant energy savings.We propose a power-efficient architecture for static random access memory(SRAM) based FPGAs,in which two modes (active mode and sleep mode) are defined for each module.In sleep mode,ultralow leakage power is consumed by the module.The module mode changes dynamically from sleep mode to active mode when module outputs evaluate for new input vectors.After producing the correct outputs,the module returns to sleep mode.The proposed circuit design reduces the leakage power consumption in both active and sleep modes.The proposed low-leakage FPGA architecture is compared with state-of-the-art architectures by implementing Microelectronics Center of North Carolina(MCNC) benchmark circuits on FPGA-SPICE software.Simulation results show an approximately 95%reduction in leakage power consumption in sleep mode.Moreover,the total power consumption (leakage+dynamic power consumption) is reduced by more than 15%compared with that of the best previous design.The average area overhead (4.26%) is less than those of other powergating designs.展开更多
基金supported in part by the National Natural Science Foundation of China(61501321,61620106001)in part by the Generic Technology Projects of the 13th Fiveyear Plan。
文摘Large scale digital beamforming(LS-DBFs)are widely used in satellite communications for spectrum reuse and transmission enhancement.SRAM-FPGAs are a popular option for software defined satellite platforms due to their rich computation resources and high flexibility.However,they are sensitive to soft errors,which limit their application in space.This paper discusses the application of coding based fault tolerance schemes for the protection of LS-DBFs on software defined payloads.Since multiple FPGAs are usually needed to support the whole LS-DBFs system,different decomposition schemes are compared in terms of resource efficiency and reliability when the coding based scheme is applied to protect the DBFs on a FPGA.Theoretical analysis and hardware experiments shows that resource efficiency and reliability are a pair of contradictory requirements for decomposition schemes.The protection with vertical decomposition could improve the reliability by 96%with 1.5x redundancy.And the protection with horizontal decomposition could improve the reliability by 85%with 1.2 x redundancy.
基金supported by the National Natural Science Foundation of China(Nos.12035019 and 11690041).
文摘For modern scaling devices,multiple cell upsets(MCUs)have become a major threat to high-reliability field-programmable gate array(FPGA)-based systems.Thus,both performing the worst-case irradiation tests to provide the actual MCU response of devices and proposing an effective MCU distinction method are urgently needed.In this study,high-and medium-energy heavy-ion irradiations for the configuration random-access memory of 28 nm FPGAs are performed.An MCU extraction method supported by theoretical predictions is proposed to study the MCU sizes,shapes,and frequencies in detail.Based on the extraction method,the different percentages,and orientations of the large MCUs in both the azimuth and zenith directions determine the worse irradiation response of the FPGAs.The extracted largest 9-bit MCUs indicate that high-energy heavy ions can induce more severe failures than medium-energy ones.The results show that both the use of high-energy heavy ions during MCU evaluations and effective protection for the application of high-density 28 nm FPGAs in space are extremely necessary.
文摘Field Programmable Gate Arrays(FPGAs)offer high capability in implementing of complex systems,and currently are an attractive solution for space system electronics.However,FPGAs are susceptible to radiation induced Single-Event Upsets(SEUs).To insure reliable operation of FPGA based systems in a harsh radiation environment,various SEU mitigation techniques have been provided.In this paper we propose a system based on dynamic partial reconfiguration capability of the modern devices to evaluate the SEU fault effect in FPGA.The proposed approach combines the fault injection controller with the host FPGA,and therefore the hardware complexity is minimized.All of the SEU injection and evaluation requirements are performed by a soft-core which realized inside the host FPGA.Experimental results on some standard benchmark circuits reveal that the proposed system is able to speed up the fault injection campaign 50 times in compared to conventional method.
基金the National Natural Science Foundation of China(Nos.12035019 and 12105339).
文摘Multiple-bit upsets(MBUs)have become a threat to modern advanced field-programmable gate arrays(FPGAs)applications in radiation environments.Hence,many investigations have been conducted using mediumenergy heavy ions to study the effects of MBU radiation.However,high-energy heavy ions(HEHIs)greatly affect the size and percentage of MBUs because their ionizationtrack structures differ from those of medium-energy heavy ions.In this study,the different impacts of high-energy and medium-energy heavy ions on MBUs in 28 nm FPGAs as well as their mechanisms are thoroughly investigated.With the Geant4 calculation,more serious energy effects of HEHIs on MBU scales were successfully demonstrated.In addition,we identified worse MBU responses resulting from lowered voltages.The MBU orientation effect was observed in the radiation of different dimensions.The broadened ionization tracks for tilted tests in different dimensions could result in different MBU sizes.The results also revealed that the ionization tracks of tilted HEHIs have more severe impacts on the MBU scales than mediumenergy heavy ions with much higher linear energy transfer.Therefore,comprehensive radiation with HEHIs is indispensable for effective hardened designs to apply highdensity 28 nm FPGAs in deep space exploration.
基金the National Natural Science Foundation of China(Nos.11079045,11179003 and 11305233)
文摘With extensive use of flash-based field-programmable gate arrays(FPGAs) in military and aerospace applications, single-event effects(SEEs) of FPGAs induced by radiations have been a major concern. In this paper, we present SEE experimental study of a flash-based FPGA from Microsemi Pro ASIC3 product family. The relation between the cross section and different linear energy transfer(LET) values for the logic tiles and embedded RAM blocks is obtained. The results show that the sequential logic cross section depends not too much on operating frequency of the device. And the relationship between 0 →1 upsets(zeros) and 1 →0 upsets(ones) is different for different kinds of D-flip-flops. The devices are not sensitive to SEL up to a LET of 99.0 Me V cm2/mg.Post-beam tests show that the programming module is damaged due to the high-LET ions.
文摘The characteristic of FPGA, motion estimation(ME) and the full search block matching arithmetic were introduced, it analyses the collectivity configuration of basic working flow in ME. Based on FPGA, the study concentrates on the control, computing and test part of ME chip implementation. In the end PCB of ME chip is designed and completed. ME is an important link of MPEG standard on picture compression, whose characteristics is its huge amount of data and computing task. So people often use special chip to meet the requirement, but there is still not such production in China at present.
文摘Routing resources are the major bottlenecks in improving the performance and power consumption of the current FPGAs. Recently reported researches have shown that carbon nanotube field effect transistors(CNFETs) have considerable potentials for improving the delay and power consumption of the modern FPGAs. In this paper, hybrid CNFET-CMOS architecture is presented for FPGAs and then this architecture is evaluated to be used in modern FPGAs. In addition, we have designed and parameterized the CNFET-based FPGA switches and calibrated them for being utilized in FPGAs at 45 nm, 22 nm and 16 nm technology nodes.Simulation results show that the CNFET-based FPGA switches improve the current FPGAs in terms of performance, power consumption and immunity to process and temperature variations. Simulation results and analyses also demonstrate that the performance of the FPGAs is improved about 30%, on average and the average and leakage power consumptions are reduced more than 6% and 98% respectively when the CNFET switches are used instead of MOSFET FPGA switches. Moreover, this technique leads to more than 20.31%smaller area. It is worth mentioning that the advantages of CNFET-based FPGAs are more considerable when the size of FPGAs grows and also when the technology node becomes smaller.
基金Supported by the National High Technology and Development Program of China(2013AA1548)
文摘An internal single event upset(SEU)mitigation technique is proposed,which reads back the configuration frames from the static random access memory(SRAM)-based field programmable gate array(FPGA)through an internal port and compares them with those stored in the radiationhardened memory to detect and correct SEUs.Triple modular redundancy(TMR),which triplicates the circuit of the technique and uses majority voters to isolate any single upset within it,is used to enhance the reliability.Performance analysis shows that the proposed technique can satisfy the requirement of ordinary aerospace missions with less power dissipation,size and weight.The fault injection experiment validates that the proposed technique is capable of correcting most errors to protect spaceborne facilities from SEUs.
基金supported by the National Natural Science Foundation of China under Grant No. 61176025 and No. 61006027the Fundamental Research Funds for the Central Universities under Grant No.ZYGX2012J003+1 种基金National Laboratory of Analogue Integrated Circuit Grants under Grant No. 9140C0901101002 and No. 9140C0901101003New Century Excellent Talents Program under Grant No.NCET-10-0297
文摘Power dissipation has become one of the key optimization conditions in logic design on field programmable gate arrays (FPGAs), thus the power estimation is necessary for logic design optimization. Nowadays, signal activity data created by logic simulation based on test vectors is essential to be used to determine the toggle rate of each signals and blocks in power estimation tools provided by field programmable gate array (FPGA) electronic design automation (EDA) tools. The accuracy of power estimation highly depends on the quality of test vectors, especially, pattern coverage. As probability distribution can describe the uncertainty signals, this work provides an algorithm which can estimate FPGAs power more effectively and accurately by using signal probability distribution rather than test vectors.
文摘Field programmable gate array (FPGA) devices have become widespread in electronic systems due to their low design costs and reconfigurability.In battery-restricted applications such as handheld electronics systems,low-power FPGAs are in great demand.Leakage power almost equals dynamic power in modern integrated circuit technologies,so the reduction of leakage power leads to significant energy savings.We propose a power-efficient architecture for static random access memory(SRAM) based FPGAs,in which two modes (active mode and sleep mode) are defined for each module.In sleep mode,ultralow leakage power is consumed by the module.The module mode changes dynamically from sleep mode to active mode when module outputs evaluate for new input vectors.After producing the correct outputs,the module returns to sleep mode.The proposed circuit design reduces the leakage power consumption in both active and sleep modes.The proposed low-leakage FPGA architecture is compared with state-of-the-art architectures by implementing Microelectronics Center of North Carolina(MCNC) benchmark circuits on FPGA-SPICE software.Simulation results show an approximately 95%reduction in leakage power consumption in sleep mode.Moreover,the total power consumption (leakage+dynamic power consumption) is reduced by more than 15%compared with that of the best previous design.The average area overhead (4.26%) is less than those of other powergating designs.
