Fifteen periods of Si/Si_(0.7)Ge_(0.3)multilayers(MLs)with various Si Ge thicknesses are grown on a 200 mm Si substrate using reduced pressure chemical vapor deposition(RPCVD).Several methods were utilized to characte...Fifteen periods of Si/Si_(0.7)Ge_(0.3)multilayers(MLs)with various Si Ge thicknesses are grown on a 200 mm Si substrate using reduced pressure chemical vapor deposition(RPCVD).Several methods were utilized to characterize and analyze the ML structures.The high resolution transmission electron microscopy(HRTEM)results show that the ML structure with 20 nm Si_(0.7)Ge_(0.3)features the best crystal quality and no defects are observed.Stacked Si_(0.7)Ge_(0.3)ML structures etched by three different methods were carried out and compared,and the results show that they have different selectivities and morphologies.In this work,the fabrication process influences on Si/Si Ge MLs are studied and there are no significant effects on the Si layers,which are the channels in lateral gate all around field effect transistor(L-GAAFET)devices.For vertically-stacked dynamic random access memory(VS-DRAM),it is necessary to consider the dislocation caused by strain accumulation and stress release after the number of stacked layers exceeds the critical thickness.These results pave the way for the manufacture of high-performance multivertical-stacked Si nanowires,nanosheet L-GAAFETs,and DRAM devices.展开更多
基金supported in part by the Strategic Priority Research Program of the Chinese Academy of Sciences (Project ID.XDA0330300)in part by Innovation Program for Quantum Science and Technology (Project ID.2021ZD0302301)in part by the Youth Innovation Promotion Association of CAS (Project ID.2020037)。
文摘Fifteen periods of Si/Si_(0.7)Ge_(0.3)multilayers(MLs)with various Si Ge thicknesses are grown on a 200 mm Si substrate using reduced pressure chemical vapor deposition(RPCVD).Several methods were utilized to characterize and analyze the ML structures.The high resolution transmission electron microscopy(HRTEM)results show that the ML structure with 20 nm Si_(0.7)Ge_(0.3)features the best crystal quality and no defects are observed.Stacked Si_(0.7)Ge_(0.3)ML structures etched by three different methods were carried out and compared,and the results show that they have different selectivities and morphologies.In this work,the fabrication process influences on Si/Si Ge MLs are studied and there are no significant effects on the Si layers,which are the channels in lateral gate all around field effect transistor(L-GAAFET)devices.For vertically-stacked dynamic random access memory(VS-DRAM),it is necessary to consider the dislocation caused by strain accumulation and stress release after the number of stacked layers exceeds the critical thickness.These results pave the way for the manufacture of high-performance multivertical-stacked Si nanowires,nanosheet L-GAAFETs,and DRAM devices.
