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Hardware Architecture of Polyphase Filter Banks Performing Embedded Resampling for Software-Defined Radio Front-Ends 被引量:3
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作者 Mehmood Awan Yannick Le Moullec +1 位作者 Peter Koch Fred Harris 《ZTE Communications》 2012年第1期54-62,70,共10页
In this paper, we describe resourceefficient hardware architectures for softwaredefined radio (SDR) frontends. These architectures are made efficient by using a polyphase channelizer that performs arbitrary sample r... In this paper, we describe resourceefficient hardware architectures for softwaredefined radio (SDR) frontends. These architectures are made efficient by using a polyphase channelizer that performs arbitrary sample rate changes, frequency selection, and bandwidth control. We discuss area, time, and power optimization for field programmable gate array (FPGA) based architectures in an Mpath polyphase filter bank with modified Npath polyphase filter. Such systems allow resampling by arbitrary ratios while simultaneously performing baseband aliasing from center frequencies at Nyquist zones that are not multiples of the output sample rate. A nonmaximally decimated polyphase filter bank, where the number of data loads is not equal to the number of M subfilters, processes M subfilters in a time period that is either less than or greater than the Mdataload ' s time period. We present a loadprocess architecture (LPA) and a runtime architecture (RA) (based on serial polyphase structure) which have different scheduling. In LPA, Nsubfilters are loaded, and then M subfilters are processed at a clock rate that is a multiple of the input data rate. This is necessary to meet the output time constraint of the down-sampled data. In RA, Msubfilters processes are efficiently scheduled within Ndataload time while simultaneously loading N subfilters. This requires reduced clock rates compared with LPA, and potentially less power is consumed. A polyphase filter bank that uses different resampling factors for maximally decimated, underdecimated, overdecimated, and combined upand downsampled scenarios is used as a case study, and an analysis of area, time, and power for their FPGA architectures is given. For resourceoptimized SDR frontends, RA is superior for reducing operating clock rates and dynamic power consumption. RA is also superior for reducing area resources, except when indices are prestored in LUTs. 展开更多
关键词 SDR FPGA Digital Frontends polyphase Filter Bank Embedded Resampling
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Polyphase Filter Banks for Embedded Sample Rate Changes in Digital Radio Front-Ends 被引量:3
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作者 Mehmood Awan Yannick Le Moullec +1 位作者 Peter Koch Fred Harris 《ZTE Communications》 2011年第4期3-9,共7页
This paper presents efficient processing engines for software-defined radio (SDR) front-ends. These engines, based on a polyphase channelizer, perform arbitrary sample-rate changes, frequency selection, and bandwidt... This paper presents efficient processing engines for software-defined radio (SDR) front-ends. These engines, based on a polyphase channelizer, perform arbitrary sample-rate changes, frequency selection, and bandwidth control. This paper presents an M-path polyphase filter bank based on a modified N-path polyphase filter. Such a system allows resampling by arbitrary ratios while performing baseband aliasing from center frequencies at Nyquist zones that are not multiples of the output sample rate. This resampling technique is based on sliding cyclic data load interacting with cyclic-shifted coefficients. A non-maximally-decimated polyphase filterbank (where the number of data loads is not equal to the number of M subfilters) processes M subfilters in a time period that is less than or greater than the M data loads. A polyphase filter bank with five different resampling modes is used as a case study for embedded resamp/ing in SDR front-ends. These modes are (i) maximally decimated, (ii) Under-decimated, (iii) over-decimated, and combined up- and down-sampling with (iv) single stride length, and (v) multiple stride lengths. These modes can be used to obtain any required rational sampling rate change in an SDR front-end based on a polyphase channelizer. They can also be used for translation to and from arbitrary center frequencies that are unrelated to the output sample rates. 展开更多
关键词 SDR digital front-ends polyphase filter bank embedded resampling
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Optimization and Synthesis of RF CMOS Polyphase Filters with Layout Considerations
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作者 张子三 马向鹏 +1 位作者 Kolnsberg Stephan Kokozinski Rainer 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2004年第12期1612-1617,共6页
A novel software tool for optimization and synthesis of RF CMOS polyhase filters(PPFs),PPFOPTIMA,is developed.In the optimization engine,genetic algorithm is adopted to avoid local optima.Experiments on PPFOPTIMA demo... A novel software tool for optimization and synthesis of RF CMOS polyhase filters(PPFs),PPFOPTIMA,is developed.In the optimization engine,genetic algorithm is adopted to avoid local optima.Experiments on PPFOPTIMA demonstrate that it is an efficient design aid for design and optimization of RF CMOS PPFs. 展开更多
关键词 RF CMOS polyphase filters quadrature signal generation genetic algorithms analog CAD
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Symbol Synchronization of Single-Carrier Signal with Ultra-Low Oversampling Rate Based on Polyphase Filter
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作者 Shili Wang Ruihao Song Dongfang Hu 《Journal of Beijing Institute of Technology》 EI CAS 2022年第5期492-504,共13页
An efficient single-carrier symbol synchronization method is proposed in this paper,which can work under a very low oversampling rate.This method is based on the frequency aliasing squared timing recovery assisted by ... An efficient single-carrier symbol synchronization method is proposed in this paper,which can work under a very low oversampling rate.This method is based on the frequency aliasing squared timing recovery assisted by pilot symbols and time domain filter.With frequency aliasing squared timing recovery with pilots,it is accessible to estimate timing error under oversampling rate less than 2.The time domain filter simultaneously performs matched-filtering and arbitrary interpolation.Because of pilot assisting,timing error estimation can be free from alias and self noise,so our method has good performance.Compared with traditional time-domain methods requiring oversampling rate above 2,this method can be adapted to any rational oversampling rate including less than 2.Moreover,compared with symbol synchronization in frequency domain which can operate under low oversampling rate,our method saves the complicated operation of conversion between time domain and frequency domain.By low oversampling rate and resource saving filter,this method is suitable for ultra-high-speed communication systems under resource-restricted hardware.The paper carries on the simulation and realization under 64QAM system.The simulation result shows that the loss is very low(less than 0.5 dB),and the real-time implementation on field programmable gate array(FPGA)also works fine. 展开更多
关键词 symbol synchronization ultra-low oversampling rate polyphase filter
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A reconfigurable low-cost memory-efficient VLSI architecture for video scaling 被引量:1
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作者 汪彦刚 Peng Silong 《High Technology Letters》 EI CAS 2013年第2期137-144,共8页
A runtime reconfigurable very-large-scale integration (VLSI) architecture for image and video scaling by arbitrary factors with good antialiasing performance is presented in this paper. Video scal- ing is used in a ... A runtime reconfigurable very-large-scale integration (VLSI) architecture for image and video scaling by arbitrary factors with good antialiasing performance is presented in this paper. Video scal- ing is used in a wide range of applications from broadcast, medical imaging and high-resolution video effects to video surveillance, and video conferencing. Many algorithms have been proposed for these applications, such as piecewise polynomial kernels and windowed sinc kernels. The sum of three shifted versions of a B-spline function, whose weights can be adjusted for different applications, is adopted as the main filter. The proposed algorithm is confirmed to be effective on image scaling ap- plications and also verified by many widely acknowledged image quality measures. The reconfigu- rable hardware architecture constitutes an arbitrary scaler with low resource consumption and high performance targeted for field programmable gate array (FPGA) devices. The scaling factor can be changed on-the-fly, and the filter can also be changed during runtime within a unifying framework. 展开更多
关键词 video scaling very-large-scale integration (VLSI) architecture polyphase filter RECONFIGURATION
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High-Speed Parallel Matched Filter Designing and FPGA Implementation
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作者 ZHANG Qinglin, CHEN Shuzhen, LUO Yijun, WANG Shan School of Electronic Information, Wuhan University, Wuhan 430072, Hubei, China 《Wuhan University Journal of Natural Sciences》 CAS 2010年第4期335-339,共5页
Matched filter is one of the key technologies to achieve high-speed data transmission. In this paper,a parallel finite-impulse response (FIR) filter structure based on polyphase filter-ing is used to achieve high-spee... Matched filter is one of the key technologies to achieve high-speed data transmission. In this paper,a parallel finite-impulse response (FIR) filter structure based on polyphase filter-ing is used to achieve high-speed matched filter in quadrature phase-shift keying (QPSK) demodulation up to 800 Mb·s-1. First,a window function is employed of to obtain impulse response of matched filter. Second,the high-speed parallel FIR structure is presented based on polyphase filtering. Then,the filter with EP2S180F1020 on the Quartus II 7.2 platform is achieved. The final results show that the design is correct and can implement high-speed matched filtering,wherein the equivalent frequency of which is up to 2 037 MHz. In addition,this scheme is easy to real-ize,which brings great value to the application of this filter in high-speed matched filters design in demodulation systems. 展开更多
关键词 parallel matched filter finite-impulse response (FIR) window function polyphase filtering field programmable gate array
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A CMOS image-rejection mixer with 58-dB IRR for DTV receivers
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作者 袁帅 李智群 +1 位作者 黄靖 王志功 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2009年第6期94-99,共6页
The design,implementation,and characterization of an image-rejection double quadrature conversion mixer based on RC asymmetric polyphase filters(PPF) are presented.The mixer consists of three sets of PPFs and a mixe... The design,implementation,and characterization of an image-rejection double quadrature conversion mixer based on RC asymmetric polyphase filters(PPF) are presented.The mixer consists of three sets of PPFs and a mixer core for quadrature down conversion.Two sets of PPFs are used for the quadrature generation and the other one is used for the IF signal selection to reject the unwanted image band.Realized in 0.18-μm CMOS technology as a part of the DVB-T receiver chip,the mixer exhibits a high image rejection ratio(IRR) of 58 dB,a power consumption of 11 mW,and a 1-dB gain compression point of-15 dBm. 展开更多
关键词 MIXER image rejection polyphase filter
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