Multi-level programmable photonic integrated circuits(PICs)and optical metasurfaces have gained widespread attention in many fields,such as neuromorphic photonics,opticalcommunications,and quantum information.In this ...Multi-level programmable photonic integrated circuits(PICs)and optical metasurfaces have gained widespread attention in many fields,such as neuromorphic photonics,opticalcommunications,and quantum information.In this paper,we propose pixelated programmable Si_(3)N_(4)PICs with record-high 20-level intermediate states at 785 nm wavelength.Such flexibility in phase or amplitude modulation is achieved by a programmable Sb_(2)S_(3)matrix,the footprint of whose elements can be as small as 1.2μm,limited only by the optical diffraction limit of anin-house developed pulsed laser writing system.We believe our work lays the foundation for laser-writing ultra-high-level(20 levels and even more)programmable photonic systems and metasurfaces based on phase change materials,which could catalyze diverse applications such as programmable neuromorphic photonics,biosensing,optical computing,photonic quantum computing,and reconfigurable metasurfaces.展开更多
Elastic metamaterials with unusual elastic properties offer unprecedented ways to modulate the polarization and propagation of elastic waves.However,most of them rely on the resonant structural components,and thus are...Elastic metamaterials with unusual elastic properties offer unprecedented ways to modulate the polarization and propagation of elastic waves.However,most of them rely on the resonant structural components,and thus are frequency-dependent and unchangeable.Here,we present a reconfigurable 2D mechanism-based metamaterial which possesses transformable and frequency-independent elastic properties.Based on the proposed mechanism-based metamaterial,interesting functionalities,such as ternarycoded elastic wave polarizer and programmable refraction,are demonstrated.Particularly,unique ternary-coded polarizers,with 1-trit polarization filtering and 2-trit polarization separating of longitudinal and transverse waves,are first achieved.Then,the strong anisotropy of the proposed metamaterial is harnessed to realize positive-negative bi-refraction,only-positive refraction,and only-negative refraction.Finally,the wave functions with detailed microstructures are numerically verified.展开更多
In this work,a novel one-time-programmable memory unit based on a Schottky-type p-GaN diode is proposed.During the programming process,the junction switches from a high-resistance state to a low-resistance state throu...In this work,a novel one-time-programmable memory unit based on a Schottky-type p-GaN diode is proposed.During the programming process,the junction switches from a high-resistance state to a low-resistance state through Schottky junction breakdown,and the state is permanently preserved.The memory unit features a current ratio of more than 10^(3),a read voltage window of 6 V,a programming time of less than 10^(−4)s,a stability of more than 108 read cycles,and a lifetime of far more than 10 years.Besides,the fabrication of the device is fully compatible with commercial Si-based GaN process platforms,which is of great significance for the realization of low-cost read-only memory in all-GaN integration.展开更多
As the country continues to promote the development of intelligent manufacturing,all industries are carrying out enterprise automation upgrading,the Pearl River Delta Intelligent Manufacturing Conference held in March...As the country continues to promote the development of intelligent manufacturing,all industries are carrying out enterprise automation upgrading,the Pearl River Delta Intelligent Manufacturing Conference held in March 2024 provides a direction guide for each enterprise on how to integrate the intelligent manufacturing technology into each link and provide direction guidance for enterprises to create new models and new business formats.College teachers,in focusing on the teaching process,should closely match the enterprise and social needs and cultivate excellent students.As the core controller of automation control,the application of programmable controllers in teaching is particularly important.In practical classes,by setting progressive difficulty,project guidance,team collaboration,and other links,students can master the automation equipment design of programmable control in repeated practice.展开更多
Chip-scale programmable optical signal processors are often used to flexibly manipulate the optical signals for satisfying the demands in various applications,such as lidar,radar,and artificial intelligence.Silicon ph...Chip-scale programmable optical signal processors are often used to flexibly manipulate the optical signals for satisfying the demands in various applications,such as lidar,radar,and artificial intelligence.Silicon photonics has unique advantages of ultra-high integration density as well as CMOS compatibility,and thus makes it possible to develop large-scale programmable optical signal processors.The challenge is the high silicon waveguides propagation losses and the high calibration complexity for all tuning elements due to the random phase errors.In this paper,we propose and demonstrate a programmable silicon photonic processor for the first time by introducing low-loss multimode photonic waveguide spirals and low-random-phase-error Mach-Zehnder switches.The present chip-scale programmable silicon photonic processor comprises a 1×4 variable power splitter based on cascaded Mach-Zehnder couplers(MZCs),four Ge/Si photodetectors,four channels of thermally-tunable optical delaylines.Each channel consists of a continuously-tuning phase shifter based on a waveguide spiral with a micro-heater and a digitally-tuning delayline realized with cascaded waveguide-spiral delaylines and MZSs for 5.68 ps time-delay step.Particularly,these waveguide spirals used here are designed to be as wide as 2μm,enabling an ultralow propagation loss of 0.28 dB/cm.Meanwhile,these MZCs and MZSs are designed with 2-μm-wide arm waveguides,and thus the random phase errors in the MZC/MZS arms are negligible,in which case the calibration for these MZSs/MZCs becomes easy and furthermore the power consumption for compensating the phase errors can be reduced greatly.Finally,this programmable silicon photonic processor is demonstrated successfully to verify a number of distinctively different functionalities,including tunable time-delay,microwave photonic beamforming,arbitrary optical signal filtering,and arbitrary waveform generation.展开更多
This article presents an integrated current mode configurable analog block(CAB)system for field-programmable analog array(FPAA).The proposed architecture is based on the complementary metal-oxide semiconductor(CMOS)tr...This article presents an integrated current mode configurable analog block(CAB)system for field-programmable analog array(FPAA).The proposed architecture is based on the complementary metal-oxide semiconductor(CMOS)transistor level design where MOSFET transistors operating in the saturation region are adopted.The proposed CAB architecture is designed to implement six of thewidely used current mode operations in analog processing systems:addition,subtraction,integration,multiplication,division,and pass operation.The functionality of the proposed CAB is demonstrated through these six operations,where each operation is chosen based on the user’s selection in the CAB interface system.The architecture of the CAB system proposes an optimized way of designing and integrating only three functional cells with the interface circuitry to achieve the six operations.Furthermore,optimized programming and digital tuning circuitry are implemented in the architecture to control and interface with the functional cells.Moreover,these designed programming and tuning circuitries play an essential role in optimizing the performance of the proposed design.Simulation of the proposed CMOS Transistor Based CAB system is carried out using Tanner EDA Tools in 0.35μm standard CMOS technology.The design uses a±1.5 V power supply and results in maximum 3 dB bandwidth of 34.9 MHz and an approximate size of 0.0537 mm2.This demonstrates the advantages of the design over the current state-of-the-art designs presented for comparison in this article.Consequently,the proposed design has a clear aspect of simplicity,low power consumption,and high bandwidth operation,which makes it a suitable candidate for mobile telecommunications applications.展开更多
Cyberattacks targeting industrial control systems(ICS)are becoming more sophisticated and advanced than in the past.A programmable logic controller(PLC),a core component of ICS,controls and monitors sensors and actuat...Cyberattacks targeting industrial control systems(ICS)are becoming more sophisticated and advanced than in the past.A programmable logic controller(PLC),a core component of ICS,controls and monitors sensors and actuators in the field.However,PLC has memory attack threats such as program injection and manipulation,which has long been a major target for attackers,and it is important to detect these attacks for ICS security.To detect PLC memory attacks,a security system is required to acquire and monitor PLC memory directly.In addition,the performance impact of the security system on the PLC makes it difficult to apply to the ICS.To address these challenges,this paper proposes a system to detect PLC memory attacks by continuously acquiring and monitoring PLC memory.The proposed system detects PLC memory attacks by acquiring the program blocks and block information directly from the same layer as the PLC and then comparing them in bytes with previous data.Experiments with Siemens S7-300 and S7-400 PLC were conducted to evaluate the PLC memory detection performance and performance impact on PLC.The experimental results demonstrate that the proposed system detects all malicious organization block(OB)injection and data block(DB)manipulation,and the increment of PLC cycle time,the impact on PLC performance,was less than 1 ms.The proposed system detects PLC memory attacks with a simpler detection method than earlier studies.Furthermore,the proposed system can be applied to ICS with a small performance impact on PLC.展开更多
A programmable multi-modulus frequency divider is designed and implemented in a 0. 35μm CMOS process. The multi-modulus frequency divider is a single chip with two dividers in series,which are divided by 4 or 5 presc...A programmable multi-modulus frequency divider is designed and implemented in a 0. 35μm CMOS process. The multi-modulus frequency divider is a single chip with two dividers in series,which are divided by 4 or 5 prescaler and by 128-255 multi-modulus frequency divider. In the circuit design, power and speed trade-offs are analyzed for the prescaler, and power optimization techniques are used according to the input frequency of each divider cell for the 128-255 multimodulus frequency divider. The chip is designed with ESD protected I/O PAD. The dividers chain can work as high as 2.4GHz with a single ended input signal and beyond 2.6GHz with differential input signals. The dual-modulus prescaler consumes 11mA of current while the 128-255 multi-modulus frequency divider consumes 17mA of current with a 3.3V power supply. The core area of the die without PAD is 0.65mm × 0.3mm. This programmable multi-modulus frequency divider can be used for 2.4GHz ISM band PLL-based frequency synthesizers. To our knowledge, this is the first reported multi-modulus frequency divider with this structure in China.展开更多
The implementation of a programmable frequency divider, which is one of the components of the phase-locked loop （PLL） frequency synthesizer for digital video broadcastingterrestrial （DVB-T） and other modem communi...The implementation of a programmable frequency divider, which is one of the components of the phase-locked loop （PLL） frequency synthesizer for digital video broadcastingterrestrial （DVB-T） and other modem communication systems, is presented. By cooperating with a dual-modulus prescaler, this divider can realize an integer frequency division from 926 to 1 387. Besides the traditional standard cell design flow, such as logic synthesis, placement and routing, the interactions between front-end and back-end are also considered to optimize the design flow under deep submicron technology. By back-annotating the back-end information to front-end design, a custom wire-load model is created which is more practical compared with the default model. This divider has been fabricated in TSMC 0. 18μm CMOS technology using Artisan standard cell library. The chip area is 675 μm × 475 μm and the power consumption is about 2 mW under a 1.8 V power supply. Measurement results show that it works correctly and can realize a frequency division with high precision.展开更多
A new approach for the design and implementation of a programmable voltage reference based on an improved current mode bandgap voltage reference is presented. The circuit is simulated and fabricated with Chartered 0....A new approach for the design and implementation of a programmable voltage reference based on an improved current mode bandgap voltage reference is presented. The circuit is simulated and fabricated with Chartered 0. 35μm mixed-signal technology. Measurements demonstrate that the temperature coefficient is ± 36. 3ppm/℃ from 0 to 100℃ when the VID inputs are 11110.As the supply voltage is varied from 2.7 to 5V, the voltage reference varies by about 5mV. The maximum glitch of the transient response is about 20mV at 125kHz. Depending on the state of the five VID inputs,an output voltage between 1.1 and 1.85V is programmed in increments of 25mV.展开更多
The drive towards shorter design cycles for analog integrated circuits has given impetus to the development of Field Programmable Analog Arrays(FPAAs),which are the analogue counterparts of Field Programmable Gate Arr...The drive towards shorter design cycles for analog integrated circuits has given impetus to the development of Field Programmable Analog Arrays(FPAAs),which are the analogue counterparts of Field Programmable Gate Arrays(FPGAs).In this paper,we present a new design methodology which using FPAA as a powerful analog front-end processing platform in the smart sensory microsystem.The proposed FPAA contains 16 homogeneous mixed-grained Configurable Analog Blocks(CABs) which house a variety of processing elements especially the proposed fine-grained Core Configurable Amplifiers(CCAs).The high flexible CABs allow the FPAA operating in both continuous-time and discrete-time approaches suitable to support variety of sensors.To reduce the nonideal parasitic effects and save area,the fat-tree interconnection network is adopted in this FPAA.The functionality of this FPAA is demonstrated through embedding of voltage and capacitive sensor signal readout circuits and a configurable band pass filter.The minimal detectable voltage and capacitor achieves 38 uV and 8.3 aF respectively within 100 Hz sensor bandwidth.The power consumption comparison of CCA in three applications shows that the FPAA has high power efficiency.And the simulation results also show that the FPAA has good tolerance with wide PVT variations.展开更多
A novel programmable gain amplifier（ PGA） based on a signal-summing topology is proposed. Different from conventional signal-summing variable gain amplifiers（ VGA）,a binary-weighted switching technique is employed...A novel programmable gain amplifier（ PGA） based on a signal-summing topology is proposed. Different from conventional signal-summing variable gain amplifiers（ VGA）,a binary-weighted switching technique is employed to vary the current-steering transistors＇ aspect ratio to change their transconductance, and hence, an accurate gain step size of 6dB is achieved. The constant-g_m biasing technique and the matching of the transistors and resistors ensures that the gain of the proposed topology is independent of the variation of process, voltage and temperature（ PVT）. P-well NMOS（ Nmetal oxide semiconductor） transistors are utilized to eliminate the influence of back-gate effect which will induce gain error.The source-degeneration technique ensures good linearity performance at a low gain. The proposed PGA is fabricated in a0.18 μm CMOS（ complementary metal oxide semiconductor）process. The measurement results show a variable gain ranging from 0 to24 dB with a step size of 6 dB and a maximum gain error of 0. 3dB. A constant 3dB bandwidth of 210 MHz is achieved at different gain settings. The measured output 3rd intercept point（OIP3） and minimum noise figure（ NF） are20. 9 dBm and 11.1 dB, respectively. The whole PGA has a compact layout of 0.068 mm^2. The total power consumption is4. 8 mW under a 1. 8 V supply voltage.展开更多
The design of a programmable frequency divider, which is one of the components of the phase-locked loop （PLL） frequency synthesizer for transmitter and receiver in IEEE 802. 11 a standard, is investigated. The main ...The design of a programmable frequency divider, which is one of the components of the phase-locked loop （PLL） frequency synthesizer for transmitter and receiver in IEEE 802. 11 a standard, is investigated. The main steps in very large-scale integration （VLSI） design flow such as logic synthesis, floorplan and placement ＆ routing （P ＆ R） are introduced. By back-annotating the back-end information to the front-end design, the custom wire-load model is created and used for optimizing the design flow under deep submicron technology. The programmable frequency divider is implemented based on Artisan TSMC （Taiwan Semicoductor Manufacturing Co. Ltd. ）0. 18μm CMOS （complementary metal-oxide-semiconductor） standard cells and fabricated. The Chip area is 1 360. 5μm^2 and can work in the range of 100 to 200 MHz. The measurement results indicate that the design conforms to the frequency division precision.展开更多
The modelling, design and implementation of a high-speed programmable polyphase finite impulse response (FIR) filter with field programmable gate array (FPGA) technology are described. This FIR filter can run automati...The modelling, design and implementation of a high-speed programmable polyphase finite impulse response (FIR) filter with field programmable gate array (FPGA) technology are described. This FIR filter can run automatically according to the programmable configuration word including symmetry/asymmetry, odd/even taps, from 32 taps up to 256 taps. The filter with 12 bit signal and 12 bit coefficient word-length has been realized on a Xilinx VirtexⅡ-v1500 device and operates at the maximum sampling frequency of (160 MHz.)展开更多
Communication-dependent and software-based distributed energy resources(DERs)are extensively integrated into modern microgrids,providing extensive benefits such as increased distributed controllability,scalability,and...Communication-dependent and software-based distributed energy resources(DERs)are extensively integrated into modern microgrids,providing extensive benefits such as increased distributed controllability,scalability,and observability.However,malicious cyber-attackers can exploit various potential vulnerabilities.In this study,a programmable adaptive security scanning(PASS)approach is presented to protect DER inverters against various power-bot attacks.Specifically,three different types of attacks,namely controller manipulation,replay,and injection attacks,are considered.This approach employs both software-defined networking technique and a novel coordinated detection method capable of enabling programmable and scalable networked microgrids(NMs)in an ultra-resilient,time-saving,and autonomous manner.The coordinated detection method efficiently identifies the location and type of power-bot attacks without disrupting normal NM operations.Extensive simulation results validate the efficacy and practicality of the PASS for securing NMs.展开更多
Targeted genome editing is a continually evolving technology employing programmable nucleases to specifically change,insert,or remove a genomic sequence of interest.These advanced molecular tools include meganucleases...Targeted genome editing is a continually evolving technology employing programmable nucleases to specifically change,insert,or remove a genomic sequence of interest.These advanced molecular tools include meganucleases,zinc finger nucleases,transcription activator-like effector nucleases and RNA-guided engineered nucleases(RGENs),which create double-strand breaks at specific target sites in the genome,and repair DNA either by homologous recombination in the presence of donor DNA or via the error-prone non-homologous end-joining mechanism.A recently discovered group of RGENs known as CRISPR/Cas9 gene-editing systems allowed precise genome manipulation revealing a causal association between disease genotype and phenotype,without the need for the reengineering of the specific enzyme when targeting different sequences.CRISPR/Cas9 has been successfully employed as an ex vivo gene-editing tool in embryonic stem cells and patient-derived stem cells to understand pancreatic beta-cell development and function.RNA-guided nucleases also open the way for the generation of novel animal models for diabetes and allow testing the efficiency of various therapeutic approaches in diabetes,as summarized and exemplified in this manuscript.展开更多
In current wireless communication and electronic systems,digital signals and electromagnetic(EM)radiation are processed by different modules.Here,we propose a mechanism to fuse the modulation of digital signals and th...In current wireless communication and electronic systems,digital signals and electromagnetic(EM)radiation are processed by different modules.Here,we propose a mechanism to fuse the modulation of digital signals and the manipulation of EM radiation on a single programmable metasurface(PM).The PM consists of massive subwavelength-scale digital coding elements.A set of digital states of all elements forms simultaneous digital information roles for modulation and the wave-control sequence code of the PM.By designing digital coding sequences in the spatial and temporal domains,the digital information and farfield patterns of the PM can be programmed simultaneously and instantly in desired ways.For the experimental demonstration of the mechanism,we present a programmable wireless communication system.The same system can realize transmissions of digital information in single-channel modes with beamsteerable capability and multichannel modes with multiple independent information.The measured results show the excellent performance of the programmable system.This work provides excellent prospects for applications in fifth-or sixth-generation wireless communications and modern intelligent platforms for unmanned aircrafts and vehicles.展开更多
We find extremely large low-magnetic-field magnetoresistance （~350% at 0.2 T and ~180% at 0.1 T） in germa- nium at room temperature and the magnetoresistanee is highly sensitive to the surface roughness. This unique...We find extremely large low-magnetic-field magnetoresistance （~350% at 0.2 T and ~180% at 0.1 T） in germa- nium at room temperature and the magnetoresistanee is highly sensitive to the surface roughness. This unique magnetoelectric property is applied to fabricate logic architecture which could perform basic Boolean logic in- cluding AND, OR, NOR and NAND. Our logic device may pave the way for a high performance microprocessor and may make the germanium family more advanced.展开更多
There are varieties of embedded systems in the world. It is a big challenge to optimize the instruction sets of System on Chips (SoCs) according to different systems' working environments. The idea of programmable...There are varieties of embedded systems in the world. It is a big challenge to optimize the instruction sets of System on Chips (SoCs) according to different systems' working environments. The idea of programmable instruction set is an effective method to gain embedded system's re-configurability. This letter presents a logic module for Java processor to be capable of using programmable instruction set. Cost (area, power, and timing) of the module is trivial. Such module is also reusable for other embedded system solutions besides Java systems.展开更多
基金funded by the National Nature Science Foundation of China(Grant Nos.52175509 and 52130504)National Key Research and Development Program of China(2017YFF0204705)2021 Postdoctoral Innovation Research Plan of Hubei Province(0106100226)。
文摘Multi-level programmable photonic integrated circuits(PICs)and optical metasurfaces have gained widespread attention in many fields,such as neuromorphic photonics,opticalcommunications,and quantum information.In this paper,we propose pixelated programmable Si_(3)N_(4)PICs with record-high 20-level intermediate states at 785 nm wavelength.Such flexibility in phase or amplitude modulation is achieved by a programmable Sb_(2)S_(3)matrix,the footprint of whose elements can be as small as 1.2μm,limited only by the optical diffraction limit of anin-house developed pulsed laser writing system.We believe our work lays the foundation for laser-writing ultra-high-level(20 levels and even more)programmable photonic systems and metasurfaces based on phase change materials,which could catalyze diverse applications such as programmable neuromorphic photonics,biosensing,optical computing,photonic quantum computing,and reconfigurable metasurfaces.
基金supported by the National Key R&D Program of China(No.2021YFE0110900)the National Natural Science Foundation of China(Nos.U22B2078 and 11991033)。
文摘Elastic metamaterials with unusual elastic properties offer unprecedented ways to modulate the polarization and propagation of elastic waves.However,most of them rely on the resonant structural components,and thus are frequency-dependent and unchangeable.Here,we present a reconfigurable 2D mechanism-based metamaterial which possesses transformable and frequency-independent elastic properties.Based on the proposed mechanism-based metamaterial,interesting functionalities,such as ternarycoded elastic wave polarizer and programmable refraction,are demonstrated.Particularly,unique ternary-coded polarizers,with 1-trit polarization filtering and 2-trit polarization separating of longitudinal and transverse waves,are first achieved.Then,the strong anisotropy of the proposed metamaterial is harnessed to realize positive-negative bi-refraction,only-positive refraction,and only-negative refraction.Finally,the wave functions with detailed microstructures are numerically verified.
基金supported in part by the National Key Research and Development Program of China under Grant 2022YFB3604400in part by the Youth Innovation Promotion Association of Chinese Academy Sciences (CAS)+4 种基金in part by the CAS-Croucher Funding Scheme under Grant CAS22801in part by National Natural Science Foundation of China under Grant 62334012, Grant 62074161, Grant 62004213, Grant U20A20208, and Grant 62304252in part by the Beijing Municipal Science and Technology Commission project under Grant Z201100008420009 and Grant Z211100007921018in part by the University of CASin part by the IMECAS-HKUST-Joint Laboratory of Microelectronics
文摘In this work,a novel one-time-programmable memory unit based on a Schottky-type p-GaN diode is proposed.During the programming process,the junction switches from a high-resistance state to a low-resistance state through Schottky junction breakdown,and the state is permanently preserved.The memory unit features a current ratio of more than 10^(3),a read voltage window of 6 V,a programming time of less than 10^(−4)s,a stability of more than 108 read cycles,and a lifetime of far more than 10 years.Besides,the fabrication of the device is fully compatible with commercial Si-based GaN process platforms,which is of great significance for the realization of low-cost read-only memory in all-GaN integration.
基金Guangdong Province Education Science Planning Project(Higher Education Special)“Construction and Practice of Applied Innovation Education System for Applied Undergraduate Mechanical Majors”(Project number:2023GXJK638)。
文摘As the country continues to promote the development of intelligent manufacturing,all industries are carrying out enterprise automation upgrading,the Pearl River Delta Intelligent Manufacturing Conference held in March 2024 provides a direction guide for each enterprise on how to integrate the intelligent manufacturing technology into each link and provide direction guidance for enterprises to create new models and new business formats.College teachers,in focusing on the teaching process,should closely match the enterprise and social needs and cultivate excellent students.As the core controller of automation control,the application of programmable controllers in teaching is particularly important.In practical classes,by setting progressive difficulty,project guidance,team collaboration,and other links,students can master the automation equipment design of programmable control in repeated practice.
基金We are grateful for financial supports from National Major Research and Development Program(No.2018YFB2200200)National Science Fund for Distinguished Young Scholars(61725503)+1 种基金Zhejiang Provincial Natural Science Foundation(LZ18F050001,LGF21F050003)National Natural Science Foundation of China(NSFC)(91950205,6191101294,11861121002,61905209,62175214,62111530147).
文摘Chip-scale programmable optical signal processors are often used to flexibly manipulate the optical signals for satisfying the demands in various applications,such as lidar,radar,and artificial intelligence.Silicon photonics has unique advantages of ultra-high integration density as well as CMOS compatibility,and thus makes it possible to develop large-scale programmable optical signal processors.The challenge is the high silicon waveguides propagation losses and the high calibration complexity for all tuning elements due to the random phase errors.In this paper,we propose and demonstrate a programmable silicon photonic processor for the first time by introducing low-loss multimode photonic waveguide spirals and low-random-phase-error Mach-Zehnder switches.The present chip-scale programmable silicon photonic processor comprises a 1×4 variable power splitter based on cascaded Mach-Zehnder couplers(MZCs),four Ge/Si photodetectors,four channels of thermally-tunable optical delaylines.Each channel consists of a continuously-tuning phase shifter based on a waveguide spiral with a micro-heater and a digitally-tuning delayline realized with cascaded waveguide-spiral delaylines and MZSs for 5.68 ps time-delay step.Particularly,these waveguide spirals used here are designed to be as wide as 2μm,enabling an ultralow propagation loss of 0.28 dB/cm.Meanwhile,these MZCs and MZSs are designed with 2-μm-wide arm waveguides,and thus the random phase errors in the MZC/MZS arms are negligible,in which case the calibration for these MZSs/MZCs becomes easy and furthermore the power consumption for compensating the phase errors can be reduced greatly.Finally,this programmable silicon photonic processor is demonstrated successfully to verify a number of distinctively different functionalities,including tunable time-delay,microwave photonic beamforming,arbitrary optical signal filtering,and arbitrary waveform generation.
基金This work was supported in part by the Geran Galakan Penyelidik Muda Grant(GGPM),Universiti Kebangsaan Malaysia,Selangor,Malaysia under grant GGPM-2021-055.
文摘This article presents an integrated current mode configurable analog block(CAB)system for field-programmable analog array(FPAA).The proposed architecture is based on the complementary metal-oxide semiconductor(CMOS)transistor level design where MOSFET transistors operating in the saturation region are adopted.The proposed CAB architecture is designed to implement six of thewidely used current mode operations in analog processing systems:addition,subtraction,integration,multiplication,division,and pass operation.The functionality of the proposed CAB is demonstrated through these six operations,where each operation is chosen based on the user’s selection in the CAB interface system.The architecture of the CAB system proposes an optimized way of designing and integrating only three functional cells with the interface circuitry to achieve the six operations.Furthermore,optimized programming and digital tuning circuitry are implemented in the architecture to control and interface with the functional cells.Moreover,these designed programming and tuning circuitries play an essential role in optimizing the performance of the proposed design.Simulation of the proposed CMOS Transistor Based CAB system is carried out using Tanner EDA Tools in 0.35μm standard CMOS technology.The design uses a±1.5 V power supply and results in maximum 3 dB bandwidth of 34.9 MHz and an approximate size of 0.0537 mm2.This demonstrates the advantages of the design over the current state-of-the-art designs presented for comparison in this article.Consequently,the proposed design has a clear aspect of simplicity,low power consumption,and high bandwidth operation,which makes it a suitable candidate for mobile telecommunications applications.
基金supported by the Korea WESTERN POWER(KOWEPO)(2022-Commissioned Research-11,Development of Cyberattack Detection Technology for New and Renewable Energy Control System Using AI(Artificial Intelligence),50%)the Institute of Information&Communications Technology Planning&Evaluation(IITP)grant funded by the Korea government(MSIT)(No.2021-0-01806,Development of Security by Design and Security Management Technology in Smart Factory,40%)the Gachon University Research Fund of 2023(GCU-202110280001,10%).
文摘Cyberattacks targeting industrial control systems(ICS)are becoming more sophisticated and advanced than in the past.A programmable logic controller(PLC),a core component of ICS,controls and monitors sensors and actuators in the field.However,PLC has memory attack threats such as program injection and manipulation,which has long been a major target for attackers,and it is important to detect these attacks for ICS security.To detect PLC memory attacks,a security system is required to acquire and monitor PLC memory directly.In addition,the performance impact of the security system on the PLC makes it difficult to apply to the ICS.To address these challenges,this paper proposes a system to detect PLC memory attacks by continuously acquiring and monitoring PLC memory.The proposed system detects PLC memory attacks by acquiring the program blocks and block information directly from the same layer as the PLC and then comparing them in bytes with previous data.Experiments with Siemens S7-300 and S7-400 PLC were conducted to evaluate the PLC memory detection performance and performance impact on PLC.The experimental results demonstrate that the proposed system detects all malicious organization block(OB)injection and data block(DB)manipulation,and the increment of PLC cycle time,the impact on PLC performance,was less than 1 ms.The proposed system detects PLC memory attacks with a simpler detection method than earlier studies.Furthermore,the proposed system can be applied to ICS with a small performance impact on PLC.
文摘A programmable multi-modulus frequency divider is designed and implemented in a 0. 35μm CMOS process. The multi-modulus frequency divider is a single chip with two dividers in series,which are divided by 4 or 5 prescaler and by 128-255 multi-modulus frequency divider. In the circuit design, power and speed trade-offs are analyzed for the prescaler, and power optimization techniques are used according to the input frequency of each divider cell for the 128-255 multimodulus frequency divider. The chip is designed with ESD protected I/O PAD. The dividers chain can work as high as 2.4GHz with a single ended input signal and beyond 2.6GHz with differential input signals. The dual-modulus prescaler consumes 11mA of current while the 128-255 multi-modulus frequency divider consumes 17mA of current with a 3.3V power supply. The core area of the die without PAD is 0.65mm × 0.3mm. This programmable multi-modulus frequency divider can be used for 2.4GHz ISM band PLL-based frequency synthesizers. To our knowledge, this is the first reported multi-modulus frequency divider with this structure in China.
基金The National Natural Science Foundation of China(No.60472057)
文摘The implementation of a programmable frequency divider, which is one of the components of the phase-locked loop （PLL） frequency synthesizer for digital video broadcastingterrestrial （DVB-T） and other modem communication systems, is presented. By cooperating with a dual-modulus prescaler, this divider can realize an integer frequency division from 926 to 1 387. Besides the traditional standard cell design flow, such as logic synthesis, placement and routing, the interactions between front-end and back-end are also considered to optimize the design flow under deep submicron technology. By back-annotating the back-end information to front-end design, a custom wire-load model is created which is more practical compared with the default model. This divider has been fabricated in TSMC 0. 18μm CMOS technology using Artisan standard cell library. The chip area is 675 μm × 475 μm and the power consumption is about 2 mW under a 1.8 V power supply. Measurement results show that it works correctly and can realize a frequency division with high precision.
文摘A new approach for the design and implementation of a programmable voltage reference based on an improved current mode bandgap voltage reference is presented. The circuit is simulated and fabricated with Chartered 0. 35μm mixed-signal technology. Measurements demonstrate that the temperature coefficient is ± 36. 3ppm/℃ from 0 to 100℃ when the VID inputs are 11110.As the supply voltage is varied from 2.7 to 5V, the voltage reference varies by about 5mV. The maximum glitch of the transient response is about 20mV at 125kHz. Depending on the state of the five VID inputs,an output voltage between 1.1 and 1.85V is programmed in increments of 25mV.
基金Supported by the CAS/SAFEA International Partnership Program for Creative Research Teams,National High Technology Research and Develop Program of China(2012AA012301)National Science and Technology Major Project of China(2013ZX03006004)
文摘The drive towards shorter design cycles for analog integrated circuits has given impetus to the development of Field Programmable Analog Arrays(FPAAs),which are the analogue counterparts of Field Programmable Gate Arrays(FPGAs).In this paper,we present a new design methodology which using FPAA as a powerful analog front-end processing platform in the smart sensory microsystem.The proposed FPAA contains 16 homogeneous mixed-grained Configurable Analog Blocks(CABs) which house a variety of processing elements especially the proposed fine-grained Core Configurable Amplifiers(CCAs).The high flexible CABs allow the FPAA operating in both continuous-time and discrete-time approaches suitable to support variety of sensors.To reduce the nonideal parasitic effects and save area,the fat-tree interconnection network is adopted in this FPAA.The functionality of this FPAA is demonstrated through embedding of voltage and capacitive sensor signal readout circuits and a configurable band pass filter.The minimal detectable voltage and capacitor achieves 38 uV and 8.3 aF respectively within 100 Hz sensor bandwidth.The power consumption comparison of CCA in three applications shows that the FPAA has high power efficiency.And the simulation results also show that the FPAA has good tolerance with wide PVT variations.
基金The National Natural Science Foundation of China(No.61306069)
文摘A novel programmable gain amplifier（ PGA） based on a signal-summing topology is proposed. Different from conventional signal-summing variable gain amplifiers（ VGA）,a binary-weighted switching technique is employed to vary the current-steering transistors＇ aspect ratio to change their transconductance, and hence, an accurate gain step size of 6dB is achieved. The constant-g_m biasing technique and the matching of the transistors and resistors ensures that the gain of the proposed topology is independent of the variation of process, voltage and temperature（ PVT）. P-well NMOS（ Nmetal oxide semiconductor） transistors are utilized to eliminate the influence of back-gate effect which will induce gain error.The source-degeneration technique ensures good linearity performance at a low gain. The proposed PGA is fabricated in a0.18 μm CMOS（ complementary metal oxide semiconductor）process. The measurement results show a variable gain ranging from 0 to24 dB with a step size of 6 dB and a maximum gain error of 0. 3dB. A constant 3dB bandwidth of 210 MHz is achieved at different gain settings. The measured output 3rd intercept point（OIP3） and minimum noise figure（ NF） are20. 9 dBm and 11.1 dB, respectively. The whole PGA has a compact layout of 0.068 mm^2. The total power consumption is4. 8 mW under a 1. 8 V supply voltage.
基金The National Natural Science Foundation of China(No60472057)
文摘The design of a programmable frequency divider, which is one of the components of the phase-locked loop （PLL） frequency synthesizer for transmitter and receiver in IEEE 802. 11 a standard, is investigated. The main steps in very large-scale integration （VLSI） design flow such as logic synthesis, floorplan and placement ＆ routing （P ＆ R） are introduced. By back-annotating the back-end information to the front-end design, the custom wire-load model is created and used for optimizing the design flow under deep submicron technology. The programmable frequency divider is implemented based on Artisan TSMC （Taiwan Semicoductor Manufacturing Co. Ltd. ）0. 18μm CMOS （complementary metal-oxide-semiconductor） standard cells and fabricated. The Chip area is 1 360. 5μm^2 and can work in the range of 100 to 200 MHz. The measurement results indicate that the design conforms to the frequency division precision.
文摘The modelling, design and implementation of a high-speed programmable polyphase finite impulse response (FIR) filter with field programmable gate array (FPGA) technology are described. This FIR filter can run automatically according to the programmable configuration word including symmetry/asymmetry, odd/even taps, from 32 taps up to 256 taps. The filter with 12 bit signal and 12 bit coefficient word-length has been realized on a Xilinx VirtexⅡ-v1500 device and operates at the maximum sampling frequency of (160 MHz.)
基金This work was supported in part by the National Science Foundation,USA(ECCS-2018492,CNS-2006828,ECCS-2002897,and OIA-2040599).
文摘Communication-dependent and software-based distributed energy resources(DERs)are extensively integrated into modern microgrids,providing extensive benefits such as increased distributed controllability,scalability,and observability.However,malicious cyber-attackers can exploit various potential vulnerabilities.In this study,a programmable adaptive security scanning(PASS)approach is presented to protect DER inverters against various power-bot attacks.Specifically,three different types of attacks,namely controller manipulation,replay,and injection attacks,are considered.This approach employs both software-defined networking technique and a novel coordinated detection method capable of enabling programmable and scalable networked microgrids(NMs)in an ultra-resilient,time-saving,and autonomous manner.The coordinated detection method efficiently identifies the location and type of power-bot attacks without disrupting normal NM operations.Extensive simulation results validate the efficacy and practicality of the PASS for securing NMs.
基金the Akdeniz University Scientific Research Commission and the Scientific and Technological Research Council of Turkey,No.TUBITAK-215S820.
文摘Targeted genome editing is a continually evolving technology employing programmable nucleases to specifically change,insert,or remove a genomic sequence of interest.These advanced molecular tools include meganucleases,zinc finger nucleases,transcription activator-like effector nucleases and RNA-guided engineered nucleases(RGENs),which create double-strand breaks at specific target sites in the genome,and repair DNA either by homologous recombination in the presence of donor DNA or via the error-prone non-homologous end-joining mechanism.A recently discovered group of RGENs known as CRISPR/Cas9 gene-editing systems allowed precise genome manipulation revealing a causal association between disease genotype and phenotype,without the need for the reengineering of the specific enzyme when targeting different sequences.CRISPR/Cas9 has been successfully employed as an ex vivo gene-editing tool in embryonic stem cells and patient-derived stem cells to understand pancreatic beta-cell development and function.RNA-guided nucleases also open the way for the generation of novel animal models for diabetes and allow testing the efficiency of various therapeutic approaches in diabetes,as summarized and exemplified in this manuscript.
基金supported by the Fund for International Cooperation and Exchange of National Natural Science Foundation of China(61761136007)the National Key Research and Development Program of China(2017YFA0700201,2017YFA0700202,and 2017YFA0700203)+3 种基金the National Natural Science Foundation of China(6217010363,61631007,61571117,61501112,61501117,61871109,61522106,61731010,61735010,61722106,61701107,and 61701108)the Natural Science Foundation of Jiangsu Province(BK20211161)the 111 Project(111-2-05)ZhiShan Young Scholar Program of Southeast University.
文摘In current wireless communication and electronic systems,digital signals and electromagnetic(EM)radiation are processed by different modules.Here,we propose a mechanism to fuse the modulation of digital signals and the manipulation of EM radiation on a single programmable metasurface(PM).The PM consists of massive subwavelength-scale digital coding elements.A set of digital states of all elements forms simultaneous digital information roles for modulation and the wave-control sequence code of the PM.By designing digital coding sequences in the spatial and temporal domains,the digital information and farfield patterns of the PM can be programmed simultaneously and instantly in desired ways.For the experimental demonstration of the mechanism,we present a programmable wireless communication system.The same system can realize transmissions of digital information in single-channel modes with beamsteerable capability and multichannel modes with multiple independent information.The measured results show the excellent performance of the programmable system.This work provides excellent prospects for applications in fifth-or sixth-generation wireless communications and modern intelligent platforms for unmanned aircrafts and vehicles.
基金Supported by the National Natural Science Foundation of China under Grant Nos 11174169,11234007 and 51471093
文摘We find extremely large low-magnetic-field magnetoresistance （~350% at 0.2 T and ~180% at 0.1 T） in germa- nium at room temperature and the magnetoresistanee is highly sensitive to the surface roughness. This unique magnetoelectric property is applied to fabricate logic architecture which could perform basic Boolean logic in- cluding AND, OR, NOR and NAND. Our logic device may pave the way for a high performance microprocessor and may make the germanium family more advanced.
基金Supported by the Guangzhou Key Technology R&D Program (No.2007Z2-D0011)
文摘There are varieties of embedded systems in the world. It is a big challenge to optimize the instruction sets of System on Chips (SoCs) according to different systems' working environments. The idea of programmable instruction set is an effective method to gain embedded system's re-configurability. This letter presents a logic module for Java processor to be capable of using programmable instruction set. Cost (area, power, and timing) of the module is trivial. Such module is also reusable for other embedded system solutions besides Java systems.
