This manuscript explores the behavior of a junctionless tri-gate FinFET at the nano-scale region using SiGe material for the channel.For the analysis,three different channel structures are used:(a)tri-layer stack chan...This manuscript explores the behavior of a junctionless tri-gate FinFET at the nano-scale region using SiGe material for the channel.For the analysis,three different channel structures are used:(a)tri-layer stack channel(TLSC)(Si-SiGe-Si),(b)double layer stack channel(DLSC)(SiGe-Si),(c)single layer channel(SLC)(S_(i)).The I−V characteristics,subthreshold swing(SS),drain-induced barrier lowering(DIBL),threshold voltage(V_(t)),drain current(ION),OFF current(IOFF),and ON-OFF current ratio(ION/IOFF)are observed for the structures at a 20 nm gate length.It is seen that TLSC provides 21.3%and 14.3%more ON current than DLSC and SLC,respectively.The paper also explores the analog and RF factors such as input transconductance(g_(m)),output transconductance(gds),gain(gm/gds),transconductance generation factor(TGF),cut-off frequency(f_(T)),maximum oscillation frequency(f_(max)),gain frequency product(GFP)and linearity performance parameters such as second and third-order harmonics(g_(m2),g_(m3)),voltage intercept points(VIP_(2),VIP_(3))and 1-dB compression points for the three structures.The results show that the TLSC has a high analog performance due to more gm and provides 16.3%,48.4%more gain than SLC and DLSC,respectively and it also provides better linearity.All the results are obtained using the VisualTCAD tool.展开更多
With the continuous development of science and technology, digital signal processing is more and more widely used in various fields. Among them, the analog-to-digital converter (ADC) is one of the key components to co...With the continuous development of science and technology, digital signal processing is more and more widely used in various fields. Among them, the analog-to-digital converter (ADC) is one of the key components to convert analog signals to digital signals. As a common type of ADC, 12-bit sequential approximation analog-to-digital converter (SAR ADC) has attracted extensive attention for its performance and application. This paper aims to conduct in-depth research and analysis of 12-bit SAR ADC to meet the growing demands of digital signal processing. This article designs a 12-bit, successive approximation analog-to-digital converter (SAR ADC) with a sampling rate of 5 MS/s. The overall circuit adopts a fully differential structure, with key modules including DAC capacitor array, comparator, and control logic. According to the DAC circuit in this paper, a fully differential capacitor DAC array structure is proposed to reduce the area of layout DAC. The comparator uses a digital dynamic comparator to improve the ADC conversion speed. The chip is designed based on the SMIC180 nm CMOS process. The simulation results show that when the sampling rate is 5 MS/s, the effective bit of SAR ADC is 11.92 bit, the SNR is 74.62 dB, and the SFDR is 89.24 dB.展开更多
This paper makes a review of state-of-thearts designs of successive-approximation register analog-to-digital converters(SAR ADCs).Methods and technique specifications are collected in view of innovative ideas.At the e...This paper makes a review of state-of-thearts designs of successive-approximation register analog-to-digital converters(SAR ADCs).Methods and technique specifications are collected in view of innovative ideas.At the end of this paper,a design example is given to illustrate the procedure to design an SAR ADC.A new method,which extends the width of the internal clock,is also proposed to facilitate different sampling frequencies,which provides more time for the digital-to-analog convert(DAC)and comparator to settle.The 10 bit ADC is simulated in 0.13 m CMOS process technology.The signal-to-noise and distortion ratio(SNDR)is 54.41 dB at a 10 MHz input with a 50MS/s sampling rate,and the power is 330 W.展开更多
A new T-shaped tunnel field-effect transistor(TTFET) with gate dielectric spacer(GDS) structure is proposed in this paper. To further studied the effects of GDS structure on the TTFET, detailed device characteristics ...A new T-shaped tunnel field-effect transistor(TTFET) with gate dielectric spacer(GDS) structure is proposed in this paper. To further studied the effects of GDS structure on the TTFET, detailed device characteristics such as current-voltage relationships, energy band diagrams, band-to-band tunneling(BTBT) rate and the magnitude of the electric field are investigated by using TCAD simulation. It is found that compared with conventional TTFET and TTFET with gate-drain overlap(GDO) structure, GDS-TTFET not only has the minimum ambipolar current but also can suppress the ambipolar current under a more extensive bias range. Furthermore, the analog/RF performances of GDS-TTFET are also investigated in terms of transconductance, gate-source capacitance, gate-drain capacitance, cutoff frequency, and gain bandwidth production. By inserting a low-κ spacer layer between the gate electrode and the gate dielectric, the GDS structure can effectively reduce parasitic capacitances between the gate and the source/drain, which leads to better performance in term of cutoff frequency and gain bandwidth production. Finally, the thickness of the gate dielectric spacer is optimized for better ambipolar current suppression and improved analog/RF performance.展开更多
A large-scale antenna system(LSAS) with digital beamforming is expected to significantly increase energy efficiency(EE) and spectral efficiency(SE) in a wireless communication system. However, there are many challengi...A large-scale antenna system(LSAS) with digital beamforming is expected to significantly increase energy efficiency(EE) and spectral efficiency(SE) in a wireless communication system. However, there are many challenging issues related to calibration, energy consumption, and cost in implementing a digital beamforming structure in an LSAS. In a practical LSAS deployment, hybrid digital-analog beamforming structures with active antennas can be used. In this paper, we investigate the optimal antenna configuration in an N × M beamforming structure, where N is the number of transceivers, M is the number of active antennas per transceiver, where analog beamforming is introduced for individual transceivers and digital beamforming is introduced across all N transceivers. We analyze the green point, which is the point of maximum EE on the EE-SE curve, and show that the log-scale EE scales linearly with SE along a slope of-lg2/N. We investigate the effect of M on EE for a given SE value in the case of fixed NM and independent N and M. In both cases, there is a unique optimal M that results in optimal EE. In the case of independent N and M, there is no optimal(N, M) combination for optimizing EE. The results of numerical simulations are provided, and these results support our analysis.展开更多
The radiation effects on several properties (reference voltage, digital output logic voltage, and supply current) of dual 8-bit analog-to-digital (A/D) converters (AD9058) under various biased conditions are investiga...The radiation effects on several properties (reference voltage, digital output logic voltage, and supply current) of dual 8-bit analog-to-digital (A/D) converters (AD9058) under various biased conditions are investigated in this paper. Gamma ray and 10-MeV proton irradiation are selected for a detailed evaluation and comparison. Based on the measurement results induced by the gamma ray with various dose rates, the devices exhibit enhanced low dose rate sensitivity (ELDRS) under zero and working bias conditions. Meanwhile, it is obvious that the ELDRS is more severe under the working bias condition than under the zero bias condition. The degradation of AD9058 does not display obvious ELDRS during 10-MeV proton irradiation with the selected flux.展开更多
There are DAC structures available in the literature for radix r = 2, 3, and 4;but how they are arrived at is missing. No general structure is available for any radix r. The aim of the paper is, therefore, to fulfil t...There are DAC structures available in the literature for radix r = 2, 3, and 4;but how they are arrived at is missing. No general structure is available for any radix r. The aim of the paper is, therefore, to fulfil these gaps. To start with, the design relations are derived for the simplest possible attenuator circuit when connected to a voltage source V and a series resistance R, such that the complete circuit offers the Thevenin resistance R. Spread relations for this attenuator are derived. An example when 3 such attenuators with different attenuation constants are connected in cascade is given. Interestingly, the two attenuators with attenuation factors 1/2 and 1/3 have the same spread of 2. A generalized attenuator is then obtained when N number of identical attenuators are connected in cascade. This is modified to derive a digital to analog converter for any radix r.展开更多
Digital circuit and analog circuit courses are basic courses for students of science and engineering universities. Among them,the practical courses are of great significance for students to master the knowledge of ele...Digital circuit and analog circuit courses are basic courses for students of science and engineering universities. Among them,the practical courses are of great significance for students to master the knowledge of electronics. In order to make teachers teaching more efficiently and students studying more quickly,how to update the experimental course in teaching reform is the key point. This paper analyzing the present situation of teaching in the digital circuit and analog circuit courses,the teaching questions in universities. On the basis of it,the innovation measures of experimental teaching methods and contents are discussed. Our school tries to introduce the UltraLab network experiment platform,reform and optimize the teaching methods of related courses.And it' s accelerating the construction and development of emerging engineering education' s process,reducing effectively the teacher's time for managing in equipment,improving the students' ability to use instruments.展开更多
We considered the physiological mechanisms of functioning of the retina’s neural network. It is marked that the primary function of a neural network is an analog-to-digital conversion of the receptor potential of pho...We considered the physiological mechanisms of functioning of the retina’s neural network. It is marked that the primary function of a neural network is an analog-to-digital conversion of the receptor potential of photoreceptor into the pulse-to-digital signal to ganglion cells. We showed the role of different types of neurons in the work of analog-to-digital converter. We gave the equivalent circuit of this converter. We researched the mechanism of the numeric coding of the receptor potential of the photoreceptor.展开更多
A digital background calibration technique that corrects the capacitor mismatches error is proposed for successive approximation register analog-to-digital converter (SAR ADC). The technique is implemented in SAR ADC ...A digital background calibration technique that corrects the capacitor mismatches error is proposed for successive approximation register analog-to-digital converter (SAR ADC). The technique is implemented in SAR ADC which is based on tri-level switching. The termination capacitor in the Digital-to-Analog Converter (DAC) is regarded as a reference capacitor and the digital weights of all other unit capacitors are corrected with respect to the reference capacitor. To make a comparison between the size of the unit capacitor and that of the reference capacitor, each input sample is quantized twice. The unit capacitor being calibrated is swapped with the reference capacitor during the second conversion. The difference between the two conversion results is used to correct the digital weight of the unit capacitor under calibration. The calibration technique with two reference capacitors is presented to reduce the number of parameters to be estimated. Behavior simulation is performed to verify the proposed calibration technique by using a 12-bit SAR ADC with 3% random capacitor mismatch. The simulation results show that the Signal-to-Noise and Distortion Ratio (SNDR) is improved from 57.2 dB to 72.2 dB and the Spurious Free Dynamic Range (SFDR) is improved from 60.0 dB to 85.4 dB.展开更多
A novel optical analog-to-digital converter based on optical time division multiplexing(OTDM) is describedwhich uses electrooptic sampling and time-demultiplexing together with multiple electronic analog-to-digitalcon...A novel optical analog-to-digital converter based on optical time division multiplexing(OTDM) is describedwhich uses electrooptic sampling and time-demultiplexing together with multiple electronic analog-to-digitalconverter(ADC). Compared with the previous scheme, the time-division multiplexer and the time-division demultiplexer areapplied in the optical analog-to-digital converter(OADC) at the same time, the design of the OADC is simplified and展开更多
An electro-absorption(EA)modulator is one of key components for optical fiber communications due to the high speed,small size,low voltage and integration ability with other semiconductor devices.A 40 Gb/s InGaAsP/InP ...An electro-absorption(EA)modulator is one of key components for optical fiber communications due to the high speed,small size,low voltage and integration ability with other semiconductor devices.A 40 Gb/s InGaAsP/InP multiplequantum-well(MQW)EA modulator monolithically integrated with a semiconductor optical amplifier(SOA)was fabricated for digital communications.The modulator capacitance was reduced to obtain 40 GHz bandwidth,and the SOA section helped reduce the insertion loss from 18 dB to 3 dB.InGaAlAs/InP MQW EA modulators have also been fabricated and characterized for analog optical fiber communications.A low driving voltage of 2.7 V and high spurious free dynamic range of 107 dB·Hz2/3 were estimated by static and dynamic measurements.展开更多
An all-optical analog-to-digital converter(ADC) based on the nonlinear effect in a silicon waveguide is a promising candidate for overcoming the limitation of electronic devices and is suitable for photonic integratio...An all-optical analog-to-digital converter(ADC) based on the nonlinear effect in a silicon waveguide is a promising candidate for overcoming the limitation of electronic devices and is suitable for photonic integration. In this paper, a lumped time-delay compensation scheme with 2-bit quantization resolution is proposed. A strip silicon waveguide is designed and used to compensate for the entire time-delays of the optical pulses after a soliton self-frequency shift(SSFS) module within a wavelength range of 1550 nm–1580 nm. A dispersion coefficient as high as-19800 ps/(km·nm) with ±0.5 ps/(km·nm)variation is predicted for the strip waveguide. The simulation results show that the maximum supportable sampling rate(MSSR) is 50.45 GSa/s with full width at half maximum(FWHM) variation less than 2.52 ps, along with the 2-bit effectivenumber-of-bit and Gray code output.展开更多
A new technique which is named charge temporary storage technique (CTST) was presented to improve the linearity of a 1.5 bit/s pipelined analog-to-digital converter (ADC). The residual voltage was obtained from the sa...A new technique which is named charge temporary storage technique (CTST) was presented to improve the linearity of a 1.5 bit/s pipelined analog-to-digital converter (ADC). The residual voltage was obtained from the sampling capacitor, and the other capacitor was just a temporary storage of charge. Then, the linearity produced by the mismatch of these capacitors was eliminated without adding extra capacitor error-averaging amplifiers. The simulation results confirmed the high linearity and low dissipation of pipelined ADCs implemented in CTST, so CTST was a new method to implement high resolution, small size ADCs.展开更多
We propose a novel lumped time-delay compensation scheme for all-optical analog-to-digital conversion based on soliton self-frequency shift and optical interconnection techniques. A linearly chirped fiber Bragg gratin...We propose a novel lumped time-delay compensation scheme for all-optical analog-to-digital conversion based on soliton self-frequency shift and optical interconnection techniques. A linearly chirped fiber Bragg grating is optimally designed and used to compensate for the entire time-delays of the quantized pulses precisely. Simulation results show that the compensated coding pulses are well synchronized with a time difference less than 3.3 ps, which can support a maximum sampling rate of 151.52 GSa/s. The proposed scheme can efficiently reduce the structure complexity and cost of all-optical analog-to-digital conversion compared to the previous schemes with multiple optical time-delay lines.展开更多
文摘This manuscript explores the behavior of a junctionless tri-gate FinFET at the nano-scale region using SiGe material for the channel.For the analysis,three different channel structures are used:(a)tri-layer stack channel(TLSC)(Si-SiGe-Si),(b)double layer stack channel(DLSC)(SiGe-Si),(c)single layer channel(SLC)(S_(i)).The I−V characteristics,subthreshold swing(SS),drain-induced barrier lowering(DIBL),threshold voltage(V_(t)),drain current(ION),OFF current(IOFF),and ON-OFF current ratio(ION/IOFF)are observed for the structures at a 20 nm gate length.It is seen that TLSC provides 21.3%and 14.3%more ON current than DLSC and SLC,respectively.The paper also explores the analog and RF factors such as input transconductance(g_(m)),output transconductance(gds),gain(gm/gds),transconductance generation factor(TGF),cut-off frequency(f_(T)),maximum oscillation frequency(f_(max)),gain frequency product(GFP)and linearity performance parameters such as second and third-order harmonics(g_(m2),g_(m3)),voltage intercept points(VIP_(2),VIP_(3))and 1-dB compression points for the three structures.The results show that the TLSC has a high analog performance due to more gm and provides 16.3%,48.4%more gain than SLC and DLSC,respectively and it also provides better linearity.All the results are obtained using the VisualTCAD tool.
文摘With the continuous development of science and technology, digital signal processing is more and more widely used in various fields. Among them, the analog-to-digital converter (ADC) is one of the key components to convert analog signals to digital signals. As a common type of ADC, 12-bit sequential approximation analog-to-digital converter (SAR ADC) has attracted extensive attention for its performance and application. This paper aims to conduct in-depth research and analysis of 12-bit SAR ADC to meet the growing demands of digital signal processing. This article designs a 12-bit, successive approximation analog-to-digital converter (SAR ADC) with a sampling rate of 5 MS/s. The overall circuit adopts a fully differential structure, with key modules including DAC capacitor array, comparator, and control logic. According to the DAC circuit in this paper, a fully differential capacitor DAC array structure is proposed to reduce the area of layout DAC. The comparator uses a digital dynamic comparator to improve the ADC conversion speed. The chip is designed based on the SMIC180 nm CMOS process. The simulation results show that when the sampling rate is 5 MS/s, the effective bit of SAR ADC is 11.92 bit, the SNR is 74.62 dB, and the SFDR is 89.24 dB.
基金supported in part by the National Natural Science Foundation of China under Grant No.61006027the New Century Excellent Talents Program of the Ministry of Education of China under Grant No.NCET-10-0297the Fundamental Research Funds for Central Universities under Grant No.ZYGX2012J003
文摘This paper makes a review of state-of-thearts designs of successive-approximation register analog-to-digital converters(SAR ADCs).Methods and technique specifications are collected in view of innovative ideas.At the end of this paper,a design example is given to illustrate the procedure to design an SAR ADC.A new method,which extends the width of the internal clock,is also proposed to facilitate different sampling frequencies,which provides more time for the digital-to-analog convert(DAC)and comparator to settle.The 10 bit ADC is simulated in 0.13 m CMOS process technology.The signal-to-noise and distortion ratio(SNDR)is 54.41 dB at a 10 MHz input with a 50MS/s sampling rate,and the power is 330 W.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61306116 and 61472322)
文摘A new T-shaped tunnel field-effect transistor(TTFET) with gate dielectric spacer(GDS) structure is proposed in this paper. To further studied the effects of GDS structure on the TTFET, detailed device characteristics such as current-voltage relationships, energy band diagrams, band-to-band tunneling(BTBT) rate and the magnitude of the electric field are investigated by using TCAD simulation. It is found that compared with conventional TTFET and TTFET with gate-drain overlap(GDO) structure, GDS-TTFET not only has the minimum ambipolar current but also can suppress the ambipolar current under a more extensive bias range. Furthermore, the analog/RF performances of GDS-TTFET are also investigated in terms of transconductance, gate-source capacitance, gate-drain capacitance, cutoff frequency, and gain bandwidth production. By inserting a low-κ spacer layer between the gate electrode and the gate dielectric, the GDS structure can effectively reduce parasitic capacitances between the gate and the source/drain, which leads to better performance in term of cutoff frequency and gain bandwidth production. Finally, the thickness of the gate dielectric spacer is optimized for better ambipolar current suppression and improved analog/RF performance.
文摘A large-scale antenna system(LSAS) with digital beamforming is expected to significantly increase energy efficiency(EE) and spectral efficiency(SE) in a wireless communication system. However, there are many challenging issues related to calibration, energy consumption, and cost in implementing a digital beamforming structure in an LSAS. In a practical LSAS deployment, hybrid digital-analog beamforming structures with active antennas can be used. In this paper, we investigate the optimal antenna configuration in an N × M beamforming structure, where N is the number of transceivers, M is the number of active antennas per transceiver, where analog beamforming is introduced for individual transceivers and digital beamforming is introduced across all N transceivers. We analyze the green point, which is the point of maximum EE on the EE-SE curve, and show that the log-scale EE scales linearly with SE along a slope of-lg2/N. We investigate the effect of M on EE for a given SE value in the case of fixed NM and independent N and M. In both cases, there is a unique optimal M that results in optimal EE. In the case of independent N and M, there is no optimal(N, M) combination for optimizing EE. The results of numerical simulations are provided, and these results support our analysis.
基金supported by the National Natural Science Foundation of China (Grant No. 11205038)the China Postdoctoral Science Foundation (Grant No. 2012M510951)
文摘The radiation effects on several properties (reference voltage, digital output logic voltage, and supply current) of dual 8-bit analog-to-digital (A/D) converters (AD9058) under various biased conditions are investigated in this paper. Gamma ray and 10-MeV proton irradiation are selected for a detailed evaluation and comparison. Based on the measurement results induced by the gamma ray with various dose rates, the devices exhibit enhanced low dose rate sensitivity (ELDRS) under zero and working bias conditions. Meanwhile, it is obvious that the ELDRS is more severe under the working bias condition than under the zero bias condition. The degradation of AD9058 does not display obvious ELDRS during 10-MeV proton irradiation with the selected flux.
文摘There are DAC structures available in the literature for radix r = 2, 3, and 4;but how they are arrived at is missing. No general structure is available for any radix r. The aim of the paper is, therefore, to fulfil these gaps. To start with, the design relations are derived for the simplest possible attenuator circuit when connected to a voltage source V and a series resistance R, such that the complete circuit offers the Thevenin resistance R. Spread relations for this attenuator are derived. An example when 3 such attenuators with different attenuation constants are connected in cascade is given. Interestingly, the two attenuators with attenuation factors 1/2 and 1/3 have the same spread of 2. A generalized attenuator is then obtained when N number of identical attenuators are connected in cascade. This is modified to derive a digital to analog converter for any radix r.
基金supported by University-level Teaching Reform Project of New Engineering,Beijing University of Chemical Technology(xgk2017040436)Teaching Reform Project of School of International Teaching,Beijing University of Chemical Technology(siejg201713)
文摘Digital circuit and analog circuit courses are basic courses for students of science and engineering universities. Among them,the practical courses are of great significance for students to master the knowledge of electronics. In order to make teachers teaching more efficiently and students studying more quickly,how to update the experimental course in teaching reform is the key point. This paper analyzing the present situation of teaching in the digital circuit and analog circuit courses,the teaching questions in universities. On the basis of it,the innovation measures of experimental teaching methods and contents are discussed. Our school tries to introduce the UltraLab network experiment platform,reform and optimize the teaching methods of related courses.And it' s accelerating the construction and development of emerging engineering education' s process,reducing effectively the teacher's time for managing in equipment,improving the students' ability to use instruments.
文摘We considered the physiological mechanisms of functioning of the retina’s neural network. It is marked that the primary function of a neural network is an analog-to-digital conversion of the receptor potential of photoreceptor into the pulse-to-digital signal to ganglion cells. We showed the role of different types of neurons in the work of analog-to-digital converter. We gave the equivalent circuit of this converter. We researched the mechanism of the numeric coding of the receptor potential of the photoreceptor.
文摘A digital background calibration technique that corrects the capacitor mismatches error is proposed for successive approximation register analog-to-digital converter (SAR ADC). The technique is implemented in SAR ADC which is based on tri-level switching. The termination capacitor in the Digital-to-Analog Converter (DAC) is regarded as a reference capacitor and the digital weights of all other unit capacitors are corrected with respect to the reference capacitor. To make a comparison between the size of the unit capacitor and that of the reference capacitor, each input sample is quantized twice. The unit capacitor being calibrated is swapped with the reference capacitor during the second conversion. The difference between the two conversion results is used to correct the digital weight of the unit capacitor under calibration. The calibration technique with two reference capacitors is presented to reduce the number of parameters to be estimated. Behavior simulation is performed to verify the proposed calibration technique by using a 12-bit SAR ADC with 3% random capacitor mismatch. The simulation results show that the Signal-to-Noise and Distortion Ratio (SNDR) is improved from 57.2 dB to 72.2 dB and the Spurious Free Dynamic Range (SFDR) is improved from 60.0 dB to 85.4 dB.
文摘A novel optical analog-to-digital converter based on optical time division multiplexing(OTDM) is describedwhich uses electrooptic sampling and time-demultiplexing together with multiple electronic analog-to-digitalconverter(ADC). Compared with the previous scheme, the time-division multiplexer and the time-division demultiplexer areapplied in the optical analog-to-digital converter(OADC) at the same time, the design of the OADC is simplified and
基金supported by National ScienceFoundation Programs(60536020,60723002)"973"State Key Basic Research Programs(2006CB302800,2006CB921106)
文摘An electro-absorption(EA)modulator is one of key components for optical fiber communications due to the high speed,small size,low voltage and integration ability with other semiconductor devices.A 40 Gb/s InGaAsP/InP multiplequantum-well(MQW)EA modulator monolithically integrated with a semiconductor optical amplifier(SOA)was fabricated for digital communications.The modulator capacitance was reduced to obtain 40 GHz bandwidth,and the SOA section helped reduce the insertion loss from 18 dB to 3 dB.InGaAlAs/InP MQW EA modulators have also been fabricated and characterized for analog optical fiber communications.A low driving voltage of 2.7 V and high spurious free dynamic range of 107 dB·Hz2/3 were estimated by static and dynamic measurements.
基金supported by the Fundamental Research Funds for the Central Universities,China(Grant No.FRF-TP-15-030A1)China Postdoctoral Science Foundation(Grant No.2015M580978)
文摘An all-optical analog-to-digital converter(ADC) based on the nonlinear effect in a silicon waveguide is a promising candidate for overcoming the limitation of electronic devices and is suitable for photonic integration. In this paper, a lumped time-delay compensation scheme with 2-bit quantization resolution is proposed. A strip silicon waveguide is designed and used to compensate for the entire time-delays of the optical pulses after a soliton self-frequency shift(SSFS) module within a wavelength range of 1550 nm–1580 nm. A dispersion coefficient as high as-19800 ps/(km·nm) with ±0.5 ps/(km·nm)variation is predicted for the strip waveguide. The simulation results show that the maximum supportable sampling rate(MSSR) is 50.45 GSa/s with full width at half maximum(FWHM) variation less than 2.52 ps, along with the 2-bit effectivenumber-of-bit and Gray code output.
基金The National Science Fund for Creative Re-search Groups( Grant No 60521002 )Shanghai Natural Science Foundation (GrantNo 037062022)
文摘A new technique which is named charge temporary storage technique (CTST) was presented to improve the linearity of a 1.5 bit/s pipelined analog-to-digital converter (ADC). The residual voltage was obtained from the sampling capacitor, and the other capacitor was just a temporary storage of charge. Then, the linearity produced by the mismatch of these capacitors was eliminated without adding extra capacitor error-averaging amplifiers. The simulation results confirmed the high linearity and low dissipation of pipelined ADCs implemented in CTST, so CTST was a new method to implement high resolution, small size ADCs.
基金Project supported by the National Basic Research Program,China(Grant Nos.2010CB327605 and 2010CB328300)the National High-Technology Research and Development Program of China(Grant No.2013AA031501)+7 种基金the National Natural Science Foundation of China(Grant No.61307109)the Specialized Research Fund for the Doctoral Program of Higher Education of China(Grant No.20120005120021)the Fundamental Research Funds for the Central Universities,China(Grant No.2013RC1202)the Program for New Century Excellent Talents in University,China(Grant No.NECT-11-0596)the Beijing Nova Program,China(Grant No.2011066)the Fund of State Key Laboratory of Information Photonics and Optical Communications(Beijing University of Posts and Telecommunications) Chinathe China Postdoctoral Science Foundation(Grant No.2012M511826)the Postdoctoral Science Foundation of Guangdong Province,China(Grant No.244331)
文摘We propose a novel lumped time-delay compensation scheme for all-optical analog-to-digital conversion based on soliton self-frequency shift and optical interconnection techniques. A linearly chirped fiber Bragg grating is optimally designed and used to compensate for the entire time-delays of the quantized pulses precisely. Simulation results show that the compensated coding pulses are well synchronized with a time difference less than 3.3 ps, which can support a maximum sampling rate of 151.52 GSa/s. The proposed scheme can efficiently reduce the structure complexity and cost of all-optical analog-to-digital conversion compared to the previous schemes with multiple optical time-delay lines.
