The base-collector depletion capacitance for vertical SiGe npn heterojunction bipolar transistors （HBTs） on silicon on insulator （SOI） is split into vertical and lateral parts. This paper proposes a novel analytic...The base-collector depletion capacitance for vertical SiGe npn heterojunction bipolar transistors （HBTs） on silicon on insulator （SOI） is split into vertical and lateral parts. This paper proposes a novel analytical depletion capacitance model of this structure for the first time. A large discrepancy is predicted when the present model is compared with the conventional depletion model, and it is shown that the capacitance decreases with the increase of the reverse collector- base bias-and shows a kink as the reverse collector-base bias reaches the effective vertical punch-through voltage while the voltage differs with the collector doping concentrations, which is consistent with measurement results. The model can be employed for a fast evaluation of the depletion capacitance of an SOI SiGe HBT and has useful applications on the design and simulation of high performance SiGe circuits and devices.展开更多
An ultracompact 3 dB coupler is designed and fabricated in silicon on insulator,based on 1×2 line tapered multimode interference (MMI) coupler.Comparing with the conventional straight MMI coupler,the device is...An ultracompact 3 dB coupler is designed and fabricated in silicon on insulator,based on 1×2 line tapered multimode interference (MMI) coupler.Comparing with the conventional straight MMI coupler,the device is ～40% shorter in length.The device exhibits uniformity of 1 3dB and excess loss of 2 5dB.展开更多
In this paper, we investigate the single event transient （SET） occurring in partially depleted silicon-on-insulator （PDSOI） metal-oxide-semiconductor （MOS） devices irradiated by pulsed laser beams. Transient sig...In this paper, we investigate the single event transient （SET） occurring in partially depleted silicon-on-insulator （PDSOI） metal-oxide-semiconductor （MOS） devices irradiated by pulsed laser beams. Transient signal characteristics of a 0.18-p.m single MOS device, such as SET pulse width, pulse maximum, and collected charge, are measured and an- alyzed at wafer level. We analyze in detail the influences of supply voltage and pulse energy on the SET characteristics of the device under test （DUT）. The dependences of SET characteristics on drain-induced barrier lowering （DIBL） and the parasitic bipolar junction transistor （PBJT） are also discussed. These results provide a guide for radiation-hardened deep sub-micrometer PDSOI technology for space electronics applications.展开更多
This paper discusses the breakdown mechanism and proposes a new simulation and test method of breakdown voltage （BV） for an ultra-high-voltage （UHV） high-side thin layer silicon-on-insulator （SOI） p-channel low-...This paper discusses the breakdown mechanism and proposes a new simulation and test method of breakdown voltage （BV） for an ultra-high-voltage （UHV） high-side thin layer silicon-on-insulator （SOI） p-channel low-density metal- oxide semiconductor （LDMOS）. Compared with the conventional simulation method, the new one is more accordant with the actual conditions of a device that can be used in the high voltage circuit. The BV of the SOI p-channel LDMOS can be properly represented and the effect of reduced bulk field can be revealed by employing the new simulation method. Simulation results show that the off-state （on-state） BV of the SOI p-channel LDMOS can reach 741 （620） V in the 3μm-thick buried oxide layer, 50μm-length drift region, and at -400 V back-gate voltage, enabling the device to be used in a 400 V UHV integrated circuit.展开更多
To overcome the floating-body effect and self-heating effect of SOI devices,the drain and source on insulator (DSOI) structure is fabricated and tested.The low dose developed recently and low energy local SIMOX techno...To overcome the floating-body effect and self-heating effect of SOI devices,the drain and source on insulator (DSOI) structure is fabricated and tested.The low dose developed recently and low energy local SIMOX technology combined with the conventional CMOS technology is used to fabricate this kind of devices.Using this method,DSOI,SOI,and bulk MOSFETs are successfully integrated on a single chip.Test results show that the drain induced barrier lowering effect is suppressed.The breakdown voltage drain-to-source is greatly increased for DSOI devices due to the elimination of the floating-body effect.And the self-heating effect is also reduced and thus the reliability increased.At the same time,the advantage of SOI devices in speed is maintained.The technology makes it possible to integrate low voltage,low power,low speed SOI devices or high voltage,high power,high speed DSOI devices on one chip and it offers option for developing system-on-chip technology.展开更多
Silicon on insulator (SOI) technology permits a good solution to the miniaturization as the MOSFET size scales down. This paper is about to compare the electrical performance of nanoscale FD-SOI MOSFET at various gate...Silicon on insulator (SOI) technology permits a good solution to the miniaturization as the MOSFET size scales down. This paper is about to compare the electrical performance of nanoscale FD-SOI MOSFET at various gate lengths. The performance is compared and contrasted with the help of threshold voltage, subthreshold slope, on-state current and leakage current. Interestingly, by decreasing the gate length, the leakage current and on-state current are increased but the threshold voltage is decreased and the sub-threshold slope is degraded. Silvaco two-dimensional simulations are used to analyze the performance of the proposed structures.展开更多
Low frequency noise behaviors of partially depleted silicon-on-insulator(PDSOI) n-channel metal-oxide semiconductors(MOS) transistors with and without ion implantation into the buried oxide are investigated in this pa...Low frequency noise behaviors of partially depleted silicon-on-insulator(PDSOI) n-channel metal-oxide semiconductors(MOS) transistors with and without ion implantation into the buried oxide are investigated in this paper. Owing to ion implantation-induced electron traps in the buried oxide and back interface states, back gate threshold voltage increases from44.48 V to 51.47 V and sub-threshold swing increases from 2.47 V/dec to 3.37 V/dec, while electron field effect mobility decreases from 475.44 cm2/V·s to 363.65 cm2/V·s. In addition, the magnitude of normalized low frequency noise also greatly increases, which indicates that the intrinsic electronic performances are degenerated after ion implantation processing. According to carrier number fluctuation theory, the extracted flat-band voltage noise power spectral densities in the PDSOI devices with and without ion implantation are equal to 7×10-10V2·Hz-1and 2.7×10-8V2·Hz-1, respectively, while the extracted average trap density in the buried oxide increases from 1.42×1017cm-3·e V-1to 6.16×1018cm-3·e V-1. Based on carrier mobility fluctuation theory, the extracted average Hooge’s parameter in these devices increases from 3.92×10-5to 1.34×10-2after ion implantation processing. Finally, radiation responses in the PDSOI devices are investigated. Owing to radiation-induced positive buried oxide trapped charges, back gate threshold voltage decreases with the increase of the total dose. After radiation reaches up to a total dose of 1 M·rad(si), the shifts of back gate threshold voltage in the SOI devices with and without ion implantation are-10.82 V and-31.84 V, respectively. The low frequency noise behaviors in these devices before and after radiation are also compared and discussed.展开更多
We have observed some kinds of defects in unseeded rapid zone-melting-recrystallized(RZMR)Si films formed with a RF-induced graphite strip heater system,using cross-section specimen electron microscope.The observed de...We have observed some kinds of defects in unseeded rapid zone-melting-recrystallized(RZMR)Si films formed with a RF-induced graphite strip heater system,using cross-section specimen electron microscope.The observed defects are subgrain boundaries(SGB),dislocations and microtwins.The most commonly observed defects are SGB which formed as a result of some orientation differences between adjacent grains during their rapid self-nucleation growth.Mixed type SGB were frequently observed,although some pure tilt or twist SGB existed also in the Si films.The rotation angular component around the axis parallel to scanning direction is much larger than that around other axes.SGB consist primarily of arrays of dislocation and have crystallographic angular deviations of one degree or less.During Si film cooling,dislocations and microtwins were formed due to non-uniform thermal stress.The crystallographic characters of the dislocations in Si films are the same as those in common bulk Si single crystals.Their Burgers vectors are b=a/2<110>.Some dis- locations run across the Si film,and the amorphous SiO_2 layers on and underneath the Si film can effectively block the dislocations and prevent them from entering the layers.Microtwins were observed in the Si films sometimes,the twinning planes being{111}.展开更多
A new type of vertical nanowire(VNW)/nanosheet(VNS)FETs combining a horizontal channel(HC)with bulk/back-gate electrode configuration,including Bulk-HC and FD-SOI-HC VNWFET,is proposed and investigated by TCAD simulat...A new type of vertical nanowire(VNW)/nanosheet(VNS)FETs combining a horizontal channel(HC)with bulk/back-gate electrode configuration,including Bulk-HC and FD-SOI-HC VNWFET,is proposed and investigated by TCAD simulation.Comparisons were carried out between conventional VNWFET and the proposed devices.FD-SOI-HC VNWFET exhibits better Ion/Ioff ratio and DIBL than Bulk-HC VNWFET.The impact of channel doping and geometric parameters on the electrical character-istic and body factor(γ)of the devices was investigated.Moreover,threshold voltage modulation by bulk/back-gate bias was im-plemented and a largeγis achieved for wide range V_(th)modulation.In addition,results of I_(on)enhancement and Ioff reduction in-dicate the proposed devices are promising candidates for performance and power optimization of NW/NS circuits by adopting dynamic threshold voltage management.The results of preliminary experimental data are discussed as well.展开更多
The annealing behavior for EL2 and EL6 groups as dominant deep levels in semi-insulating GaAs was presented using Photo Induced Transient Spectroscopy measurement (PITS). During rapid thermal annealing, a relation was...The annealing behavior for EL2 and EL6 groups as dominant deep levels in semi-insulating GaAs was presented using Photo Induced Transient Spectroscopy measurement (PITS). During rapid thermal annealing, a relation was identified between EL2 group at 0.79 and 0.82 eV and EL6 group at 0.24, 0.27 and 0.82 eV below the conduction band. It is found that they may be close in structure, and belong to the EL2 and EL6 groups, respectively. In rapidly annealed samples, the quantity of all defects in the EL2 group increases, while that in the EL6 group decreases. However, by furnace annealing at 950°C for 5 h, some of the defects in the EL2 group break up, and the quantity of all defects in the EL6 group increases. It is suggested that the EL2 group and EL6 group are related in their microscopy structures. The relation between the two groups and origins was also discussed.展开更多
A new analytical model for the surface electric field distribution and breakdown voltage of the silicon oil insulator （SOI） trench lateral double-diffused metal-oxide-semiconductor （LDMOS） is presented. Based on t...A new analytical model for the surface electric field distribution and breakdown voltage of the silicon oil insulator （SOI） trench lateral double-diffused metal-oxide-semiconductor （LDMOS） is presented. Based on the two-dimensional Laplace solution and Poisson solution, the model considers the influence of structure parameters such as the doping concentration of the drift region, and the depth and width of the trench on the surface electric field. Further, a simple analytical expression of the breakdown voltage is obtained, which offers an effective way to gain an optimal high voltage. All the analytical results are in good agreement with the simulation results.展开更多
In this study, we investigate the single-event transient（SET） characteristics of a partially depleted silicon-on-insulator（PDSOI） metal-oxide-semiconductor（MOS） device induced by a pulsed laser.We measure and an...In this study, we investigate the single-event transient（SET） characteristics of a partially depleted silicon-on-insulator（PDSOI） metal-oxide-semiconductor（MOS） device induced by a pulsed laser.We measure and analyze the drain transient current at the wafer level. The results indicate that the body-drain junction and its vicinity are more SET sensitive than the other regions in PD-SOI devices.We use ISE 3D simulation tools to analyze the SET response when different regions of the device are hit. Then, we discuss in detail the characteristics of transient currents and the electrostatic potential distribution change in devices after irradiation. Finally, we analyze the parasitic bipolar junction transistor（p-BJT） effect by performing both a laser test and simulations.展开更多
A simple method to fabricate vertically coupled micro-ring resonators in amorphous silicon-on-insulator is created by a three-step lithography process. First, the linear loss at 1.55 μm of the a-Si：H film is calcula...A simple method to fabricate vertically coupled micro-ring resonators in amorphous silicon-on-insulator is created by a three-step lithography process. First, the linear loss at 1.55 μm of the a-Si：H film is calculated to be 0.2 =k 0.05 dB/cm. Then, the bottom line waveguide of Su-8 with a flat top surface of 300 nm is created by etching. The thickness of Su-8 can easily be controlled by the etching time. Finally, by opening the window pattern and etching several layers, the first layer marks made by electron beam lithography are found with a 50 nm resolution, and the high quality of the micro-ring resonator is demonstrated.展开更多
This paper presents a high-responsivity and high-speed InGaAs/InP PIN photodetector integrated onto the silicon waveguide substrate utilizing the divinyltetramethyldisiloxane-benzocyclobutene （DVS-BCB） adhesive bond...This paper presents a high-responsivity and high-speed InGaAs/InP PIN photodetector integrated onto the silicon waveguide substrate utilizing the divinyltetramethyldisiloxane-benzocyclobutene （DVS-BCB） adhesive bonding method. A grating coupler is adopted to couple light from the fiber to the silicon waveguide. Light in the silicon photonic waveguide is evanescently coupled into the photodetector. The integrated photodetector structure is first simulated using the FDTD （finite difference time domain） solutions software and the simulation results show a detection efficiency of 95%. According to the simulation result, the integrated photodetector is fabricated. The measured responsivity of the fabricated integrated photodetector with a detection length of 30μm is 0.89 A/W excluding the coupling loss between the fiber and the grating coupler and the silicon propagation loss at the wave-length of 1550 nm with a reverse bias voltage of 3 V. Measured 3-dB bandwidth is 27 GHz using the Lightwave Component Analyzer （LCA）. The eye diagram signal test results indicate that the photodetector can operate at a high speed of 40 Gbit/s. The integrated photodetector is of great significance in the silicon-based optoelectronic integrated chip which can be applied to the optical communication and the super node data transmission chip of the high-performance computer.展开更多
In this paper, we present simulation results of an electrooptical variable optical attenuator (VOA) integrated in silicon-on-insulator waveguide. The device is functionally based on free carriers absorption to achieve...In this paper, we present simulation results of an electrooptical variable optical attenuator (VOA) integrated in silicon-on-insulator waveguide. The device is functionally based on free carriers absorption to achieve attenuation. Beam propagation method (BPM) and two-dimensional semiconductor device simulation tool PISCES-II were used to analyze the dc and transient characteristics of the device. The device has a response time (including rise time and fall time) less than 200 ns, much faster than the thermooptic and micro-electromechanical systems (MEMSs) based VOAs.展开更多
A novel and simple polarization independent grating couplers is designed and analyzed here, in which the TE polarization and the TM polarization light can be simultaneously coupled into a silicon waveguide along the s...A novel and simple polarization independent grating couplers is designed and analyzed here, in which the TE polarization and the TM polarization light can be simultaneously coupled into a silicon waveguide along the same direction with high coupling efficiency. For the polarization-insensitive grating coupler, the coupling effi- ciencies of two orthogonal polarizations light are more than 60% at 1550 nm wavelength based on our optimized design parameters including grating period, etching height, filling factor, and so on. For TE mode the maximum efficiency is ~72% with more than 30 nm i dB bandwidth, simultaneously, for TM mode the maximum efficiency is 75.15% with 40 nm 1 dB bandwidth. Their corresponding wavelength difference between two polarizations＇ coupling peaks is demonstrated to be 35 nm. Polarization independent grating coupler designed here can be widelv used in optical communication and ontical information processing.展开更多
The tensile strained Ge/SiGe multiple quantum wells （MQWs） grown on a silicon-on-insulator （SOI） substrate were fabricated successfully by ultra-high chemical vapor deposition. Room temperature direct band photolu...The tensile strained Ge/SiGe multiple quantum wells （MQWs） grown on a silicon-on-insulator （SOI） substrate were fabricated successfully by ultra-high chemical vapor deposition. Room temperature direct band photoluminescence from Ge quantum wells on SOI substrate is strongly modulated by Fabry-Perot cavity formed between the surface of Ge and the interface of buried SiO2. The photoluminescence peak intensity at 1.58 μm is enhanced by about 21 times compared with that from the Ge/SiGe quantum wells on Si substrate, and the full width at half maximum （FWHM） is significantly reduced. It is suggested that tensile strained Ge/SiGe multiple quantum wells are one of the promising materials for Si-based microcavity lijzht emitting devices.展开更多
Device structure and fabrication process of SOI nMOSFET depleted partially are p roposed for multi-gigahertz RF applications.Many advanced techniques for deep submiron MOSFETs are incorporated into the proposed devic...Device structure and fabrication process of SOI nMOSFET depleted partially are p roposed for multi-gigahertz RF applications.Many advanced techniques for deep submiron MOSFETs are incorporated into the proposed device.Main steps and condit ions in process are given in details,with simulation and optimization by using t he process simulator,Tsuprem4.Experiment results of 0.25μm SOI RF nMOSFET are i n consistence with simulated ones,and excellent or acceptable parameters of devi ce performance are obtained for multi-gigahertz RF applications.展开更多
Modeling analysis of thin fully depleted SOICMOS technology has been done. Using ISETCAD software,the high temperature characteristics of an SOICMOS transistor were simulated in the temperature range of from 300 to 60...Modeling analysis of thin fully depleted SOICMOS technology has been done. Using ISETCAD software,the high temperature characteristics of an SOICMOS transistor were simulated in the temperature range of from 300 to 600K, and the whole circuit of a laser range finder was simulated with Verilog software. By wafer pro- cessing,a circuit of a laser range finder with complete function and parameters working at high temperatures has been developed. The simulated results agree with the test results. The test of the circuit function and parameters at normal and high temperature shows the realization of an SOICMOS integrated circuit with low power dissipation and high speed, which can be applied in laser range finding. By manufacturing this device, further study on high temperature characteristics of shorter channel SOICMOS integrated circuits can be conducted.展开更多
By using silicon-on-insulator(SOI) platform, 12 channel waveguides, and four parallel-coupling one-microring resonator routing elements, a non-blocking four-port optical router is proposed. Structure design and optimi...By using silicon-on-insulator(SOI) platform, 12 channel waveguides, and four parallel-coupling one-microring resonator routing elements, a non-blocking four-port optical router is proposed. Structure design and optimization are performed on the routing elements at 1 550 nm. At drop state with a power consumption of 0 m W, the insertion loss of the drop port is less than 1.12 d B, and the crosstalk between the two output ports is less than-28 d B; at through state with a power consumption of 22 m W, the insertion loss of the through port is less than 0.45 d B, and the crosstalk between the two output ports is below-21 d B. Routing topology and function are demonstrated for the four-port optical router. The router can work at nine non-blocking routing states using the thermo-optic(TO) effect of silicon for tuning the resonance of each switching element. Detailed characterizations are presented, including output spectrum, insertion loss, and crosstalk. According to the analysis on all the data links of the router, the insertion loss is within the range of 0.13—3.36 d B, and the crosstalk is less than-19.46 d B. The router can meet the need of large-scale optical network-on-chip(ONo C).展开更多
基金Project supported by the National Ministries and Commissions(Grant Nos.51308040203,72105499,and6139801)
文摘The base-collector depletion capacitance for vertical SiGe npn heterojunction bipolar transistors （HBTs） on silicon on insulator （SOI） is split into vertical and lateral parts. This paper proposes a novel analytical depletion capacitance model of this structure for the first time. A large discrepancy is predicted when the present model is compared with the conventional depletion model, and it is shown that the capacitance decreases with the increase of the reverse collector- base bias-and shows a kink as the reverse collector-base bias reaches the effective vertical punch-through voltage while the voltage differs with the collector doping concentrations, which is consistent with measurement results. The model can be employed for a fast evaluation of the depletion capacitance of an SOI SiGe HBT and has useful applications on the design and simulation of high performance SiGe circuits and devices.
文摘An ultracompact 3 dB coupler is designed and fabricated in silicon on insulator,based on 1×2 line tapered multimode interference (MMI) coupler.Comparing with the conventional straight MMI coupler,the device is ～40% shorter in length.The device exhibits uniformity of 1 3dB and excess loss of 2 5dB.
文摘In this paper, we investigate the single event transient （SET） occurring in partially depleted silicon-on-insulator （PDSOI） metal-oxide-semiconductor （MOS） devices irradiated by pulsed laser beams. Transient signal characteristics of a 0.18-p.m single MOS device, such as SET pulse width, pulse maximum, and collected charge, are measured and an- alyzed at wafer level. We analyze in detail the influences of supply voltage and pulse energy on the SET characteristics of the device under test （DUT）. The dependences of SET characteristics on drain-induced barrier lowering （DIBL） and the parasitic bipolar junction transistor （PBJT） are also discussed. These results provide a guide for radiation-hardened deep sub-micrometer PDSOI technology for space electronics applications.
基金Project supported by the National Natural Science Foundation of China (Grant No. 60906038)
文摘This paper discusses the breakdown mechanism and proposes a new simulation and test method of breakdown voltage （BV） for an ultra-high-voltage （UHV） high-side thin layer silicon-on-insulator （SOI） p-channel low-density metal- oxide semiconductor （LDMOS）. Compared with the conventional simulation method, the new one is more accordant with the actual conditions of a device that can be used in the high voltage circuit. The BV of the SOI p-channel LDMOS can be properly represented and the effect of reduced bulk field can be revealed by employing the new simulation method. Simulation results show that the off-state （on-state） BV of the SOI p-channel LDMOS can reach 741 （620） V in the 3μm-thick buried oxide layer, 50μm-length drift region, and at -400 V back-gate voltage, enabling the device to be used in a 400 V UHV integrated circuit.
文摘To overcome the floating-body effect and self-heating effect of SOI devices,the drain and source on insulator (DSOI) structure is fabricated and tested.The low dose developed recently and low energy local SIMOX technology combined with the conventional CMOS technology is used to fabricate this kind of devices.Using this method,DSOI,SOI,and bulk MOSFETs are successfully integrated on a single chip.Test results show that the drain induced barrier lowering effect is suppressed.The breakdown voltage drain-to-source is greatly increased for DSOI devices due to the elimination of the floating-body effect.And the self-heating effect is also reduced and thus the reliability increased.At the same time,the advantage of SOI devices in speed is maintained.The technology makes it possible to integrate low voltage,low power,low speed SOI devices or high voltage,high power,high speed DSOI devices on one chip and it offers option for developing system-on-chip technology.
文摘Silicon on insulator (SOI) technology permits a good solution to the miniaturization as the MOSFET size scales down. This paper is about to compare the electrical performance of nanoscale FD-SOI MOSFET at various gate lengths. The performance is compared and contrasted with the help of threshold voltage, subthreshold slope, on-state current and leakage current. Interestingly, by decreasing the gate length, the leakage current and on-state current are increased but the threshold voltage is decreased and the sub-threshold slope is degraded. Silvaco two-dimensional simulations are used to analyze the performance of the proposed structures.
基金supported by the National Natural Science Foundation of China(Grant Nos.61204112 and 61204116)
文摘Low frequency noise behaviors of partially depleted silicon-on-insulator(PDSOI) n-channel metal-oxide semiconductors(MOS) transistors with and without ion implantation into the buried oxide are investigated in this paper. Owing to ion implantation-induced electron traps in the buried oxide and back interface states, back gate threshold voltage increases from44.48 V to 51.47 V and sub-threshold swing increases from 2.47 V/dec to 3.37 V/dec, while electron field effect mobility decreases from 475.44 cm2/V·s to 363.65 cm2/V·s. In addition, the magnitude of normalized low frequency noise also greatly increases, which indicates that the intrinsic electronic performances are degenerated after ion implantation processing. According to carrier number fluctuation theory, the extracted flat-band voltage noise power spectral densities in the PDSOI devices with and without ion implantation are equal to 7×10-10V2·Hz-1and 2.7×10-8V2·Hz-1, respectively, while the extracted average trap density in the buried oxide increases from 1.42×1017cm-3·e V-1to 6.16×1018cm-3·e V-1. Based on carrier mobility fluctuation theory, the extracted average Hooge’s parameter in these devices increases from 3.92×10-5to 1.34×10-2after ion implantation processing. Finally, radiation responses in the PDSOI devices are investigated. Owing to radiation-induced positive buried oxide trapped charges, back gate threshold voltage decreases with the increase of the total dose. After radiation reaches up to a total dose of 1 M·rad(si), the shifts of back gate threshold voltage in the SOI devices with and without ion implantation are-10.82 V and-31.84 V, respectively. The low frequency noise behaviors in these devices before and after radiation are also compared and discussed.
基金This research is supported by the National Science Foundatinon of China.
文摘We have observed some kinds of defects in unseeded rapid zone-melting-recrystallized(RZMR)Si films formed with a RF-induced graphite strip heater system,using cross-section specimen electron microscope.The observed defects are subgrain boundaries(SGB),dislocations and microtwins.The most commonly observed defects are SGB which formed as a result of some orientation differences between adjacent grains during their rapid self-nucleation growth.Mixed type SGB were frequently observed,although some pure tilt or twist SGB existed also in the Si films.The rotation angular component around the axis parallel to scanning direction is much larger than that around other axes.SGB consist primarily of arrays of dislocation and have crystallographic angular deviations of one degree or less.During Si film cooling,dislocations and microtwins were formed due to non-uniform thermal stress.The crystallographic characters of the dislocations in Si films are the same as those in common bulk Si single crystals.Their Burgers vectors are b=a/2<110>.Some dis- locations run across the Si film,and the amorphous SiO_2 layers on and underneath the Si film can effectively block the dislocations and prevent them from entering the layers.Microtwins were observed in the Si films sometimes,the twinning planes being{111}.
基金supported by the Academy of Integrated Circuit Innovation of Chinese Academy of Sciences under grant No Y7YC01X001。
文摘A new type of vertical nanowire(VNW)/nanosheet(VNS)FETs combining a horizontal channel(HC)with bulk/back-gate electrode configuration,including Bulk-HC and FD-SOI-HC VNWFET,is proposed and investigated by TCAD simulation.Comparisons were carried out between conventional VNWFET and the proposed devices.FD-SOI-HC VNWFET exhibits better Ion/Ioff ratio and DIBL than Bulk-HC VNWFET.The impact of channel doping and geometric parameters on the electrical character-istic and body factor(γ)of the devices was investigated.Moreover,threshold voltage modulation by bulk/back-gate bias was im-plemented and a largeγis achieved for wide range V_(th)modulation.In addition,results of I_(on)enhancement and Ioff reduction in-dicate the proposed devices are promising candidates for performance and power optimization of NW/NS circuits by adopting dynamic threshold voltage management.The results of preliminary experimental data are discussed as well.
文摘The annealing behavior for EL2 and EL6 groups as dominant deep levels in semi-insulating GaAs was presented using Photo Induced Transient Spectroscopy measurement (PITS). During rapid thermal annealing, a relation was identified between EL2 group at 0.79 and 0.82 eV and EL6 group at 0.24, 0.27 and 0.82 eV below the conduction band. It is found that they may be close in structure, and belong to the EL2 and EL6 groups, respectively. In rapidly annealed samples, the quantity of all defects in the EL2 group increases, while that in the EL6 group decreases. However, by furnace annealing at 950°C for 5 h, some of the defects in the EL2 group break up, and the quantity of all defects in the EL6 group increases. It is suggested that the EL2 group and EL6 group are related in their microscopy structures. The relation between the two groups and origins was also discussed.
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 61176069 and 60976060)the National Key Laboratory of Analogue Integrated Circuit, China (Grant No. 9140C090304110C0905)
文摘A new analytical model for the surface electric field distribution and breakdown voltage of the silicon oil insulator （SOI） trench lateral double-diffused metal-oxide-semiconductor （LDMOS） is presented. Based on the two-dimensional Laplace solution and Poisson solution, the model considers the influence of structure parameters such as the doping concentration of the drift region, and the depth and width of the trench on the surface electric field. Further, a simple analytical expression of the breakdown voltage is obtained, which offers an effective way to gain an optimal high voltage. All the analytical results are in good agreement with the simulation results.
基金Project supported by Funds of Key Laboratory,China(Grant No.y7ys011001)Youth Innovation Promotion Association,Chinese Academy of Sciences(Grant No.y5yq01r002)
文摘In this study, we investigate the single-event transient（SET） characteristics of a partially depleted silicon-on-insulator（PDSOI） metal-oxide-semiconductor（MOS） device induced by a pulsed laser.We measure and analyze the drain transient current at the wafer level. The results indicate that the body-drain junction and its vicinity are more SET sensitive than the other regions in PD-SOI devices.We use ISE 3D simulation tools to analyze the SET response when different regions of the device are hit. Then, we discuss in detail the characteristics of transient currents and the electrostatic potential distribution change in devices after irradiation. Finally, we analyze the parasitic bipolar junction transistor（p-BJT） effect by performing both a laser test and simulations.
基金supported by the National Natural Science Foundation of China (No. 11172042)the financial support from the China Scholarship Council for her joint Ph.D scholarship (No. 201306030017)supported by the Centre for Ultrahigh Bandwidth Devices for Optical Systems, Laser Physics Centre, Research School of Physics and Engineering, Australian National University, Canberra ACT2600, Australia
文摘A simple method to fabricate vertically coupled micro-ring resonators in amorphous silicon-on-insulator is created by a three-step lithography process. First, the linear loss at 1.55 μm of the a-Si：H film is calculated to be 0.2 =k 0.05 dB/cm. Then, the bottom line waveguide of Su-8 with a flat top surface of 300 nm is created by etching. The thickness of Su-8 can easily be controlled by the etching time. Finally, by opening the window pattern and etching several layers, the first layer marks made by electron beam lithography are found with a 50 nm resolution, and the high quality of the micro-ring resonator is demonstrated.
基金Project supported by the High-Tech Research and Development Program of China(Nos.2015AA016904,2015AA012302)the National Basic Research Program of China(Nos.2012CB933503,2013CB932904)the National Natural Foundation of China(Nos.61274069,61176053,61021003,61435002)
文摘This paper presents a high-responsivity and high-speed InGaAs/InP PIN photodetector integrated onto the silicon waveguide substrate utilizing the divinyltetramethyldisiloxane-benzocyclobutene （DVS-BCB） adhesive bonding method. A grating coupler is adopted to couple light from the fiber to the silicon waveguide. Light in the silicon photonic waveguide is evanescently coupled into the photodetector. The integrated photodetector structure is first simulated using the FDTD （finite difference time domain） solutions software and the simulation results show a detection efficiency of 95%. According to the simulation result, the integrated photodetector is fabricated. The measured responsivity of the fabricated integrated photodetector with a detection length of 30μm is 0.89 A/W excluding the coupling loss between the fiber and the grating coupler and the silicon propagation loss at the wave-length of 1550 nm with a reverse bias voltage of 3 V. Measured 3-dB bandwidth is 27 GHz using the Lightwave Component Analyzer （LCA）. The eye diagram signal test results indicate that the photodetector can operate at a high speed of 40 Gbit/s. The integrated photodetector is of great significance in the silicon-based optoelectronic integrated chip which can be applied to the optical communication and the super node data transmission chip of the high-performance computer.
基金This work was supported by the National Natural Science Foundation of China under Grant Nos. 69896260 and 69990540, and the "973" Project by the National Science and Technology Ministry under Contract No. G20000366. Q. Yan's e-mail address is qfyan@red.s
文摘In this paper, we present simulation results of an electrooptical variable optical attenuator (VOA) integrated in silicon-on-insulator waveguide. The device is functionally based on free carriers absorption to achieve attenuation. Beam propagation method (BPM) and two-dimensional semiconductor device simulation tool PISCES-II were used to analyze the dc and transient characteristics of the device. The device has a response time (including rise time and fall time) less than 200 ns, much faster than the thermooptic and micro-electromechanical systems (MEMSs) based VOAs.
基金supported by the National Natural Science Foundation of China(No.60907003)the Foundation of NUDT(No.JC13-02-13)+1 种基金the Hunan Provincial Natural Science Foundation of China(No.13JJ3001)the Program for New Century Excellent Talents in University(No.NCET-12-0142)
文摘A novel and simple polarization independent grating couplers is designed and analyzed here, in which the TE polarization and the TM polarization light can be simultaneously coupled into a silicon waveguide along the same direction with high coupling efficiency. For the polarization-insensitive grating coupler, the coupling effi- ciencies of two orthogonal polarizations light are more than 60% at 1550 nm wavelength based on our optimized design parameters including grating period, etching height, filling factor, and so on. For TE mode the maximum efficiency is ~72% with more than 30 nm i dB bandwidth, simultaneously, for TM mode the maximum efficiency is 75.15% with 40 nm 1 dB bandwidth. Their corresponding wavelength difference between two polarizations＇ coupling peaks is demonstrated to be 35 nm. Polarization independent grating coupler designed here can be widelv used in optical communication and ontical information processing.
基金supported by the National Natural Science Foundation of China(Nos.61036003 and 61176092)the Ph.D.Programs Foundation of Ministry of Education of China(No.20110121110025)
文摘The tensile strained Ge/SiGe multiple quantum wells （MQWs） grown on a silicon-on-insulator （SOI） substrate were fabricated successfully by ultra-high chemical vapor deposition. Room temperature direct band photoluminescence from Ge quantum wells on SOI substrate is strongly modulated by Fabry-Perot cavity formed between the surface of Ge and the interface of buried SiO2. The photoluminescence peak intensity at 1.58 μm is enhanced by about 21 times compared with that from the Ge/SiGe quantum wells on Si substrate, and the full width at half maximum （FWHM） is significantly reduced. It is suggested that tensile strained Ge/SiGe multiple quantum wells are one of the promising materials for Si-based microcavity lijzht emitting devices.
文摘Device structure and fabrication process of SOI nMOSFET depleted partially are p roposed for multi-gigahertz RF applications.Many advanced techniques for deep submiron MOSFETs are incorporated into the proposed device.Main steps and condit ions in process are given in details,with simulation and optimization by using t he process simulator,Tsuprem4.Experiment results of 0.25μm SOI RF nMOSFET are i n consistence with simulated ones,and excellent or acceptable parameters of devi ce performance are obtained for multi-gigahertz RF applications.
文摘Modeling analysis of thin fully depleted SOICMOS technology has been done. Using ISETCAD software,the high temperature characteristics of an SOICMOS transistor were simulated in the temperature range of from 300 to 600K, and the whole circuit of a laser range finder was simulated with Verilog software. By wafer pro- cessing,a circuit of a laser range finder with complete function and parameters working at high temperatures has been developed. The simulated results agree with the test results. The test of the circuit function and parameters at normal and high temperature shows the realization of an SOICMOS integrated circuit with low power dissipation and high speed, which can be applied in laser range finding. By manufacturing this device, further study on high temperature characteristics of shorter channel SOICMOS integrated circuits can be conducted.
基金supported by the National Natural Science Foundation of China(Nos.61107021 and 61177027)the Ministry of Education of China(Nos.20110061120052 and 20120061130008)+2 种基金the China Postdoctoral Science Foundation(Nos.20110491299 and 2012T50297)the Science and Technology Department of Jilin Province of China(No.20130522161JH)the Special Funds of Basic Science and Technology of Jilin University(No.201103076)
文摘By using silicon-on-insulator(SOI) platform, 12 channel waveguides, and four parallel-coupling one-microring resonator routing elements, a non-blocking four-port optical router is proposed. Structure design and optimization are performed on the routing elements at 1 550 nm. At drop state with a power consumption of 0 m W, the insertion loss of the drop port is less than 1.12 d B, and the crosstalk between the two output ports is less than-28 d B; at through state with a power consumption of 22 m W, the insertion loss of the through port is less than 0.45 d B, and the crosstalk between the two output ports is below-21 d B. Routing topology and function are demonstrated for the four-port optical router. The router can work at nine non-blocking routing states using the thermo-optic(TO) effect of silicon for tuning the resonance of each switching element. Detailed characterizations are presented, including output spectrum, insertion loss, and crosstalk. According to the analysis on all the data links of the router, the insertion loss is within the range of 0.13—3.36 d B, and the crosstalk is less than-19.46 d B. The router can meet the need of large-scale optical network-on-chip(ONo C).
