The difference between circuit design stage and time requirements has broadened with the increasing complexity of the circuit.A big database is needed to undertake important analytical work like statistical method,hea...The difference between circuit design stage and time requirements has broadened with the increasing complexity of the circuit.A big database is needed to undertake important analytical work like statistical method,heat research,and IR-drop research that results in extended running times.This unit focuses on the assessment of test strength.Because of the enormous number of successful designs for currentmodels and the unnecessary time required for every test,maximum energy ratings with all tests cannot be achieved.Nevertheless,test safety is important for producing trustworthy findings to avoid loss of output and harm to the chip.Generally,effective power assessment is only possible in a limited sample of pre-selected experiments.Thus,a key objective is to find the experiments that might give the worst situations again for testing power.It offers a machine-based circuit power estimation(MLCPE)system for the selection of exams.Two distinct techniques of predicting are utilized.Firstly,to find testings with power dissipation,it forecasts the behavior of testing.Secondly,the changemovement and energy data are linked to the semiconductor design,identifying small problem areas.Several types of algorithms are utilized.In particular,the methods compared.The findings show great accuracy and efficiency in forecasting.That enables such methods suitable for selecting the worst scenario.展开更多
Continuous improvements in very-large-scale integration(VLSI)technology and design software have significantly broadened the scope of digital signal processing(DSP)applications.The use of application-specific integrat...Continuous improvements in very-large-scale integration(VLSI)technology and design software have significantly broadened the scope of digital signal processing(DSP)applications.The use of application-specific integrated circuits(ASICs)and programmable digital signal processors for many DSP applications have changed,even though new system implementations based on reconfigurable computing are becoming more complex.Adaptable platforms that combine hardware and software programmability efficiency are rapidly maturing with discrete wavelet transformation(DWT)and sophisticated computerized design techniques,which are much needed in today’s modern world.New research and commercial efforts to sustain power optimization,cost savings,and improved runtime effectiveness have been initiated as initial reconfigurable technologies have emerged.Hence,in this paper,it is proposed that theDWTmethod can be implemented on a fieldprogrammable gate array in a digital architecture(FPGA-DA).We examined the effects of quantization on DWTperformance in classification problems to demonstrate its reliability concerning fixed-point math implementations.The Advanced Encryption Standard(AES)algorithm for DWT learning used in this architecture is less responsive to resampling errors than the previously proposed solution in the literature using the artificial neural networks(ANN)method.By reducing hardware area by 57%,the proposed system has a higher throughput rate of 88.72%,reliability analysis of 95.5%compared to the other standard methods.展开更多
现代视频编码标准普遍采用变换与运动补偿预测混合型编码架构,该架构对运动补偿预测后的残差图像和运动矢量等信息进行变换编码,运动补偿预测的准确度对编码性能有显著影响.由于实际对象的运动精度是任意小的,允许运动矢量具有“分像素...现代视频编码标准普遍采用变换与运动补偿预测混合型编码架构,该架构对运动补偿预测后的残差图像和运动矢量等信息进行变换编码,运动补偿预测的准确度对编码性能有显著影响.由于实际对象的运动精度是任意小的,允许运动矢量具有“分像素”精度,可以有效地提高运动补偿预测准确度,为了得到“分像素”位置的像素值,需要参考其周围相邻的像素值进行插值滤波.文中提出了一种低空间复杂度1/4像素插值方法两步四抽头插值法(Two Steps Four Taps Interpolation,TSFT),该方法与目前国际上最先进的视频编码标准H.264/AVC相比,可以降低11%的空间复杂度,计算复杂度和编码效率相当,已经被国内制定的编码标准AVS1.0采纳.另外,分像素插值是解码端主要的访存和计算瓶颈,文中给出了一个基于多级流水线结构的VLSI实现结构,可以降低访存带宽,同时提高插值器的运算速度,满足高清视频实时解码的需要.展开更多
基金supported by Dr S Karthik,SRM Institute of Science and TechnologySRM Institute of Science and Technology,Vadapalani Campus,Chennai,Tamilnadu,India。
文摘The difference between circuit design stage and time requirements has broadened with the increasing complexity of the circuit.A big database is needed to undertake important analytical work like statistical method,heat research,and IR-drop research that results in extended running times.This unit focuses on the assessment of test strength.Because of the enormous number of successful designs for currentmodels and the unnecessary time required for every test,maximum energy ratings with all tests cannot be achieved.Nevertheless,test safety is important for producing trustworthy findings to avoid loss of output and harm to the chip.Generally,effective power assessment is only possible in a limited sample of pre-selected experiments.Thus,a key objective is to find the experiments that might give the worst situations again for testing power.It offers a machine-based circuit power estimation(MLCPE)system for the selection of exams.Two distinct techniques of predicting are utilized.Firstly,to find testings with power dissipation,it forecasts the behavior of testing.Secondly,the changemovement and energy data are linked to the semiconductor design,identifying small problem areas.Several types of algorithms are utilized.In particular,the methods compared.The findings show great accuracy and efficiency in forecasting.That enables such methods suitable for selecting the worst scenario.
基金This work was supported by King Saud University for funding this work through Researchers Supporting Project number(RSP-2021/387),King Saud University,Riyadh,Saudi Arabia。
文摘Continuous improvements in very-large-scale integration(VLSI)technology and design software have significantly broadened the scope of digital signal processing(DSP)applications.The use of application-specific integrated circuits(ASICs)and programmable digital signal processors for many DSP applications have changed,even though new system implementations based on reconfigurable computing are becoming more complex.Adaptable platforms that combine hardware and software programmability efficiency are rapidly maturing with discrete wavelet transformation(DWT)and sophisticated computerized design techniques,which are much needed in today’s modern world.New research and commercial efforts to sustain power optimization,cost savings,and improved runtime effectiveness have been initiated as initial reconfigurable technologies have emerged.Hence,in this paper,it is proposed that theDWTmethod can be implemented on a fieldprogrammable gate array in a digital architecture(FPGA-DA).We examined the effects of quantization on DWTperformance in classification problems to demonstrate its reliability concerning fixed-point math implementations.The Advanced Encryption Standard(AES)algorithm for DWT learning used in this architecture is less responsive to resampling errors than the previously proposed solution in the literature using the artificial neural networks(ANN)method.By reducing hardware area by 57%,the proposed system has a higher throughput rate of 88.72%,reliability analysis of 95.5%compared to the other standard methods.
文摘现代视频编码标准普遍采用变换与运动补偿预测混合型编码架构,该架构对运动补偿预测后的残差图像和运动矢量等信息进行变换编码,运动补偿预测的准确度对编码性能有显著影响.由于实际对象的运动精度是任意小的,允许运动矢量具有“分像素”精度,可以有效地提高运动补偿预测准确度,为了得到“分像素”位置的像素值,需要参考其周围相邻的像素值进行插值滤波.文中提出了一种低空间复杂度1/4像素插值方法两步四抽头插值法(Two Steps Four Taps Interpolation,TSFT),该方法与目前国际上最先进的视频编码标准H.264/AVC相比,可以降低11%的空间复杂度,计算复杂度和编码效率相当,已经被国内制定的编码标准AVS1.0采纳.另外,分像素插值是解码端主要的访存和计算瓶颈,文中给出了一个基于多级流水线结构的VLSI实现结构,可以降低访存带宽,同时提高插值器的运算速度,满足高清视频实时解码的需要.
