The advantages of the all-fiber optical current transformer include but are not limited to being small in size,having no magnetic saturation,exhibiting high measurement accuracy,and boasting strong electromagnetic int...The advantages of the all-fiber optical current transformer include but are not limited to being small in size,having no magnetic saturation,exhibiting high measurement accuracy,and boasting strong electromagnetic interference resistance.However,the high cost of the all-fiber optical transformer limits its promotion and application in engineering.This paper proposes a design scheme of an independent double acquisition loop for the all-fiber optical current transformer based on the single optical path.Firstly,based on the closed-loop control mode and open-loop control mode,the twochannel sampling signal demand for relay protection,and the independent dual-acquisition loop design scheme of the all-fiber optical current transformer are proposed.Secondly,the reliability and economic feasibility of the scheme are demonstrated by an analysis of system failure and cost.The results show that the scheme can actualize the acquisition function of two independent all-fiber optical current transformer products on a single all-fiber current transformer in an integrated manner,which greatly reduces the cost of the all-fiber optical current transformer in engineering applications.展开更多
High-speed,fixed-latency serial links find application in distributed data acquisition and control systems,such as the timing trigger and control(TTC)system for high energy physics experiments.However,most high-speed ...High-speed,fixed-latency serial links find application in distributed data acquisition and control systems,such as the timing trigger and control(TTC)system for high energy physics experiments.However,most high-speed serial transceivers do not keep the same chip latency after each power-up or reset,as there is no deterministic phase relationship between the transmitted and received clocks after each power-up.In this paper,we propose a fixed-latency serial link based on high-speed transceivers embedded in Xilinx field programmable gate arrays(FPGAs).First,we modify the configuration and clock distribution of the transceiver to eliminate the phase difference between the clock domains in the transmitter/receiver.Second,we use the internal alignment circuit of the transceiver and a digital clock manager(DCM)/phase-locked loop(PLL)based clock generator to eliminate the phase difference between the clock domains in the transmitter and receiver.The test results of the link latency are shown.Compared with existing solutions,our design not only implements fixed chip latency,but also reduces the average system lock time.展开更多
基金supported by the National Natural Science Foundation of China (No. U1866203)
文摘The advantages of the all-fiber optical current transformer include but are not limited to being small in size,having no magnetic saturation,exhibiting high measurement accuracy,and boasting strong electromagnetic interference resistance.However,the high cost of the all-fiber optical transformer limits its promotion and application in engineering.This paper proposes a design scheme of an independent double acquisition loop for the all-fiber optical current transformer based on the single optical path.Firstly,based on the closed-loop control mode and open-loop control mode,the twochannel sampling signal demand for relay protection,and the independent dual-acquisition loop design scheme of the all-fiber optical current transformer are proposed.Secondly,the reliability and economic feasibility of the scheme are demonstrated by an analysis of system failure and cost.The results show that the scheme can actualize the acquisition function of two independent all-fiber optical current transformer products on a single all-fiber current transformer in an integrated manner,which greatly reduces the cost of the all-fiber optical current transformer in engineering applications.
基金Project supported by the National Science and Technology Support Program of China(No.2012BAK24B01)the Fundamental Research Funds for the Central Universities,China(No.N100204001)+1 种基金the Specialized Research Fund for the Doctoral Program of Higher Edu-cation,China(No.20110042110021)the National Science Foundation for Post-doctoral Scientists of China(No.2013M541243)
文摘High-speed,fixed-latency serial links find application in distributed data acquisition and control systems,such as the timing trigger and control(TTC)system for high energy physics experiments.However,most high-speed serial transceivers do not keep the same chip latency after each power-up or reset,as there is no deterministic phase relationship between the transmitted and received clocks after each power-up.In this paper,we propose a fixed-latency serial link based on high-speed transceivers embedded in Xilinx field programmable gate arrays(FPGAs).First,we modify the configuration and clock distribution of the transceiver to eliminate the phase difference between the clock domains in the transmitter/receiver.Second,we use the internal alignment circuit of the transceiver and a digital clock manager(DCM)/phase-locked loop(PLL)based clock generator to eliminate the phase difference between the clock domains in the transmitter and receiver.The test results of the link latency are shown.Compared with existing solutions,our design not only implements fixed chip latency,but also reduces the average system lock time.
