The paper presents a new architecture composed of bit plane-parallel coder for Embedded Block Coding with Optimized Truncation (EBCOT) entropy encoder used in JPEG2000. In the architecture, the coding information of e...The paper presents a new architecture composed of bit plane-parallel coder for Embedded Block Coding with Optimized Truncation (EBCOT) entropy encoder used in JPEG2000. In the architecture, the coding information of each bit plane can be obtained simultaneously and processed parallel. Compared with other architectures, it has advantages of high parallelism, and no waste clock cycles for a single point. The experimental results show that it reduces the processing time about 86% than that of bit plane sequential scheme. A Field Programmable Gate Array (FPGA) prototype chip is designed and simulation results show that it can process 512×512 gray-scaled images with more than 30 frames per second at 52MHz.展开更多
Fractal encoding technique possesses some particular properties which make it as an attractive approach to video sequences compression. In this paper, we propose a novel fractal based encoding method for video signal...Fractal encoding technique possesses some particular properties which make it as an attractive approach to video sequences compression. In this paper, we propose a novel fractal based encoding method for video signals, which, based on Self Transformation Systems( STS ), is combined with Motion Compensation as well as nonlinear transformation. Experiment of results of realtime image sequences show that the proposed method can achieve a very fast encoding speed and acceptable tradeoff between compression ration and decoding quality.展开更多
基金Supported in part by the "863" Program (No.2003 AA1ZB10)
文摘The paper presents a new architecture composed of bit plane-parallel coder for Embedded Block Coding with Optimized Truncation (EBCOT) entropy encoder used in JPEG2000. In the architecture, the coding information of each bit plane can be obtained simultaneously and processed parallel. Compared with other architectures, it has advantages of high parallelism, and no waste clock cycles for a single point. The experimental results show that it reduces the processing time about 86% than that of bit plane sequential scheme. A Field Programmable Gate Array (FPGA) prototype chip is designed and simulation results show that it can process 512×512 gray-scaled images with more than 30 frames per second at 52MHz.
文摘Fractal encoding technique possesses some particular properties which make it as an attractive approach to video sequences compression. In this paper, we propose a novel fractal based encoding method for video signals, which, based on Self Transformation Systems( STS ), is combined with Motion Compensation as well as nonlinear transformation. Experiment of results of realtime image sequences show that the proposed method can achieve a very fast encoding speed and acceptable tradeoff between compression ration and decoding quality.
