A high integrated monolithic IC, with functions of clock recovery, data decision, and 1 ： 4 demultiplexer,is implemented in 0.25μm CMOS process for 2.5Gb/s fiber-optic communications. The recovered and frequency div...A high integrated monolithic IC, with functions of clock recovery, data decision, and 1 ： 4 demultiplexer,is implemented in 0.25μm CMOS process for 2.5Gb/s fiber-optic communications. The recovered and frequency divided 625MHz clock has a phase noise of -106.26dBc/Hz at 100kHz offset in response to a 2.5Gb/s PRBS input data （2^31-1）. The 2.5Gb/s PRBS data are demultiplexed to four 625Mb/s data. The 0.97mm× 0.97mm IC consumes 550mW under a single 3.3V power supply （not including output buffers）.展开更多
A 2.5Gb/s clock and data recovery （CDR） circuit is designed and realized in TSMC＇s standard 0.18/μm CMOS process. The clock recovery is based on a PLL. For phase noise optimization,a dynamic phase and frequency de...A 2.5Gb/s clock and data recovery （CDR） circuit is designed and realized in TSMC＇s standard 0.18/μm CMOS process. The clock recovery is based on a PLL. For phase noise optimization,a dynamic phase and frequency detector （PFD） is used in the PLL. The rms jitter of the recovered 2.5GHz clock is 2.4ps and the SSB phase noise is - 111dBc/Hz at 10kHz offset. The rms jitter of the recovered 2.5Gb/s data is 3.3ps. The power consumption is 120mW.展开更多
The design of a 2. 488 Gbit/s clock and data recovery （CDR） If for synchronous digital hierarchy （SDH） STM-16 receiver is described. Based on the injected phase-locked loop （IPLL） and D-flip flop architectures, ...The design of a 2. 488 Gbit/s clock and data recovery （CDR） If for synchronous digital hierarchy （SDH） STM-16 receiver is described. Based on the injected phase-locked loop （IPLL） and D-flip flop architectures, the CDR IC was implemented in a standard 0. 35 μan complementary metal-oxide-semiconductor （CMOS） technology. With 2^31 -1 pseudorandom bit sequences （PRBS） input, the sensitivity of data recovery circuit is less than 20 mV with 10^-12 bit error rate （BER）. The recovered clock shows a root mean square （rms） jitter of 2. 8 ps and a phase noise of - 110 dBc/Hz at 100 kHz offset. The capture range of the circuit is larger than 40 MHz. With a 5 V supply, the circuit consumes 680 mW and the chip area is 1.49 mm × 1 mm.展开更多
In this paper,a detailed analysis of a phase interpolator for clock recovery is presented. A mathematical model is setup for the phase interpolator and we perform a precise analysis using this model. The result shows ...In this paper,a detailed analysis of a phase interpolator for clock recovery is presented. A mathematical model is setup for the phase interpolator and we perform a precise analysis using this model. The result shows that the output amplitude and linearity of phase interpolator is primarily related to the difference between the two input phases. A new encoding pattern is given to solve this problem. Analysis in the circuit domain was also undertaken. The simulation results show that the relation between RC time-constant and time difference of input clocks affects the linearity of the phase interpolator. To alleviate this undesired effect, two adjustable-RC buffers are added at the input of the PI. Finally,a 90nm CMOS phase interpolator,which can work in the frequency from 1GHz to 5GHz,is proposed. The power dissipation of the phase interpolator is lmW with a 1.2V power supply. Experiment results show that the phase interpolator has a monotone output phase and good linearity.展开更多
A 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver(TRx)designed in a 28-nm complementary metal-oxide-semiconduc-tor(CMOS)process is presented in this article.A voltage-mode(VM)driver featuring a 4-tap reconfigurable feed-fo...A 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver(TRx)designed in a 28-nm complementary metal-oxide-semiconduc-tor(CMOS)process is presented in this article.A voltage-mode(VM)driver featuring a 4-tap reconfigurable feed-forward equal-izer(FFE)is employed in the quarter-rate transmitter(TX).The half-rate receiver(RX)incorporates a continuous-time linear equal-izer(CTLE),a 3-stage high-speed slicer with multi-clock-phase sampling,and a clock and data recovery(CDR).The experimen-tal results show that the TRx operates at a maximum speed of 56 Gb/s with chip-on board(COB)assembly.The 28 Gb/s NRZ eye diagram shows a far-end vertical eye opening of 210 mV with an output amplitude of 351 mV single-ended and the 56 Gb/s PAM-4 eye diagram exhibits far-end eye opening of 33 mV(upper-eye),31 mV(mid-eye),and 28 mV(lower-eye)with an output amplitude of 353 mV single-ended.The recovered 14 GHz clock from the RX exhibits random jitter(RJ)of 469 fs and deterministic jitter(DJ)of 8.76 ps.The 875 Mb/s de-multiplexed data features 593 ps horizontal eye opening with 32.02 ps RJ,at bit-error rate(BER)of 10-5(0.53 UI).The power dissipation of TX and RX are 125 and 181.4 mW,respectively,from a 0.9-V sup-ply.展开更多
To improve the performance of composite pseudo-noise （PN） code clock recovery in a regenerative PN ranging system at a low symbol signal-to-noise ratio （SNR）, a novel chip tracking loop （CTL） used for regenerati...To improve the performance of composite pseudo-noise （PN） code clock recovery in a regenerative PN ranging system at a low symbol signal-to-noise ratio （SNR）, a novel chip tracking loop （CTL） used for regenerative PN ranging clock recovery is adopted. The CTL is a modified data transition tracking loop （DTTL）. The difference between them is that the Q channel output of the CTL is directly multiplied by a clock component, while that of the DTTL is multiplied by the Ⅰ channel transition detector output. Under the condition of a quasi-squareware PN ranging code, the tracking （ mean square timing jitter） performance of the CTL is analyzed. The tracking performances of the CTL and the DTTL, are compared over a wide range of symbol SNRs. The result shows that the CTL and the DTTL have the same performance at a large symbol SNR, while at a low symbol SNR, the former offers a noticeable enhancement.展开更多
The need for wide-band clock and data recovery （CDR） circuits is discussed. A 2 Gbps to 12 Gbps continuous-rate CDR circuit employing a multi-mode voltage-control oscillator （VCO）, a frequency detector, and a phas...The need for wide-band clock and data recovery （CDR） circuits is discussed. A 2 Gbps to 12 Gbps continuous-rate CDR circuit employing a multi-mode voltage-control oscillator （VCO）, a frequency detector, and a phase detector （FD＆PD） is described. A new automatic frequency band selection （FBS） without external reference clock is proposed to select the appropriate mode and also solve the instability problem when the circuit is powering on. The multi-mode VCO and FD/PD circuits which can operate at full-rate and half-rate modes facilitate CDR with six operation modes. The proposed CDR structure has been modeled with MATLAB and the simulated results validate its feasibility.展开更多
Phase locked loop(PLL) is a typical analog-digital mixed signal circuit and a method of conducting a top level system verification including PLL with standard digital simulator becomes especially significant.The behav...Phase locked loop(PLL) is a typical analog-digital mixed signal circuit and a method of conducting a top level system verification including PLL with standard digital simulator becomes especially significant.The behavioral level model(BLM) of the PLL in Verilog-HDL for pure digital simulator is innovated in this paper,and the design of PLL based clock and data recovery(CDR)circuit aided with jitter attenuation PLL for SerDes application is also presented.The CDR employs a dual-loop architecture where a frequency-locked loop acts as an acquisition aid to the phase-locked loop.To simultaneously meet jitter tolerance and jitter transfer specifications defined in G.8251 of optical transport network(ITU-T OTN),an additional jitter attenuation PLL is used.Simulation results show that the peak-to-peak jitter of the recovered clock and data is 5.17 ps and 2.3ps respectively.The core of the whole chip consumes 72 mA current from a 1.0V supply.展开更多
文摘A high integrated monolithic IC, with functions of clock recovery, data decision, and 1 ： 4 demultiplexer,is implemented in 0.25μm CMOS process for 2.5Gb/s fiber-optic communications. The recovered and frequency divided 625MHz clock has a phase noise of -106.26dBc/Hz at 100kHz offset in response to a 2.5Gb/s PRBS input data （2^31-1）. The 2.5Gb/s PRBS data are demultiplexed to four 625Mb/s data. The 0.97mm× 0.97mm IC consumes 550mW under a single 3.3V power supply （not including output buffers）.
文摘A 2.5Gb/s clock and data recovery （CDR） circuit is designed and realized in TSMC＇s standard 0.18/μm CMOS process. The clock recovery is based on a PLL. For phase noise optimization,a dynamic phase and frequency detector （PFD） is used in the PLL. The rms jitter of the recovered 2.5GHz clock is 2.4ps and the SSB phase noise is - 111dBc/Hz at 10kHz offset. The rms jitter of the recovered 2.5Gb/s data is 3.3ps. The power consumption is 120mW.
文摘The design of a 2. 488 Gbit/s clock and data recovery （CDR） If for synchronous digital hierarchy （SDH） STM-16 receiver is described. Based on the injected phase-locked loop （IPLL） and D-flip flop architectures, the CDR IC was implemented in a standard 0. 35 μan complementary metal-oxide-semiconductor （CMOS） technology. With 2^31 -1 pseudorandom bit sequences （PRBS） input, the sensitivity of data recovery circuit is less than 20 mV with 10^-12 bit error rate （BER）. The recovered clock shows a root mean square （rms） jitter of 2. 8 ps and a phase noise of - 110 dBc/Hz at 100 kHz offset. The capture range of the circuit is larger than 40 MHz. With a 5 V supply, the circuit consumes 680 mW and the chip area is 1.49 mm × 1 mm.
文摘In this paper,a detailed analysis of a phase interpolator for clock recovery is presented. A mathematical model is setup for the phase interpolator and we perform a precise analysis using this model. The result shows that the output amplitude and linearity of phase interpolator is primarily related to the difference between the two input phases. A new encoding pattern is given to solve this problem. Analysis in the circuit domain was also undertaken. The simulation results show that the relation between RC time-constant and time difference of input clocks affects the linearity of the phase interpolator. To alleviate this undesired effect, two adjustable-RC buffers are added at the input of the PI. Finally,a 90nm CMOS phase interpolator,which can work in the frequency from 1GHz to 5GHz,is proposed. The power dissipation of the phase interpolator is lmW with a 1.2V power supply. Experiment results show that the phase interpolator has a monotone output phase and good linearity.
基金supported by National Natural Science Foundation of China under Grant 62174132the Fundamental Research Funds for Central Universities under Grant xzy022022060.
文摘A 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver(TRx)designed in a 28-nm complementary metal-oxide-semiconduc-tor(CMOS)process is presented in this article.A voltage-mode(VM)driver featuring a 4-tap reconfigurable feed-forward equal-izer(FFE)is employed in the quarter-rate transmitter(TX).The half-rate receiver(RX)incorporates a continuous-time linear equal-izer(CTLE),a 3-stage high-speed slicer with multi-clock-phase sampling,and a clock and data recovery(CDR).The experimen-tal results show that the TRx operates at a maximum speed of 56 Gb/s with chip-on board(COB)assembly.The 28 Gb/s NRZ eye diagram shows a far-end vertical eye opening of 210 mV with an output amplitude of 351 mV single-ended and the 56 Gb/s PAM-4 eye diagram exhibits far-end eye opening of 33 mV(upper-eye),31 mV(mid-eye),and 28 mV(lower-eye)with an output amplitude of 353 mV single-ended.The recovered 14 GHz clock from the RX exhibits random jitter(RJ)of 469 fs and deterministic jitter(DJ)of 8.76 ps.The 875 Mb/s de-multiplexed data features 593 ps horizontal eye opening with 32.02 ps RJ,at bit-error rate(BER)of 10-5(0.53 UI).The power dissipation of TX and RX are 125 and 181.4 mW,respectively,from a 0.9-V sup-ply.
文摘To improve the performance of composite pseudo-noise （PN） code clock recovery in a regenerative PN ranging system at a low symbol signal-to-noise ratio （SNR）, a novel chip tracking loop （CTL） used for regenerative PN ranging clock recovery is adopted. The CTL is a modified data transition tracking loop （DTTL）. The difference between them is that the Q channel output of the CTL is directly multiplied by a clock component, while that of the DTTL is multiplied by the Ⅰ channel transition detector output. Under the condition of a quasi-squareware PN ranging code, the tracking （ mean square timing jitter） performance of the CTL is analyzed. The tracking performances of the CTL and the DTTL, are compared over a wide range of symbol SNRs. The result shows that the CTL and the DTTL have the same performance at a large symbol SNR, while at a low symbol SNR, the former offers a noticeable enhancement.
基金supported by the Hubei Natural Science Foundation of China underGrant No. 2010CDB02706the Fundamental Research Funds for the Central Universities under Grant No. C2009Q060
文摘The need for wide-band clock and data recovery （CDR） circuits is discussed. A 2 Gbps to 12 Gbps continuous-rate CDR circuit employing a multi-mode voltage-control oscillator （VCO）, a frequency detector, and a phase detector （FD＆PD） is described. A new automatic frequency band selection （FBS） without external reference clock is proposed to select the appropriate mode and also solve the instability problem when the circuit is powering on. The multi-mode VCO and FD/PD circuits which can operate at full-rate and half-rate modes facilitate CDR with six operation modes. The proposed CDR structure has been modeled with MATLAB and the simulated results validate its feasibility.
基金Supported by the National High Technology Research and Development Programme of China(No.2011AA010301)the Research Foundation of Zhongxing Telecom Equipment Corporation and the National Natural Science Foundation of China(No.60976029)
文摘Phase locked loop(PLL) is a typical analog-digital mixed signal circuit and a method of conducting a top level system verification including PLL with standard digital simulator becomes especially significant.The behavioral level model(BLM) of the PLL in Verilog-HDL for pure digital simulator is innovated in this paper,and the design of PLL based clock and data recovery(CDR)circuit aided with jitter attenuation PLL for SerDes application is also presented.The CDR employs a dual-loop architecture where a frequency-locked loop acts as an acquisition aid to the phase-locked loop.To simultaneously meet jitter tolerance and jitter transfer specifications defined in G.8251 of optical transport network(ITU-T OTN),an additional jitter attenuation PLL is used.Simulation results show that the peak-to-peak jitter of the recovered clock and data is 5.17 ps and 2.3ps respectively.The core of the whole chip consumes 72 mA current from a 1.0V supply.
