The development of large-scale quantum computing has boosted anurgent desire for the advancement of cryogenic CMOS(cryo-CMOS),which is a promising scalable solution for the control and read-out interface of quantum bi...The development of large-scale quantum computing has boosted anurgent desire for the advancement of cryogenic CMOS(cryo-CMOS),which is a promising scalable solution for the control and read-out interface of quantum bits.In the current work,180 nm CMOS transistors were characterized and modeled down to 4 K,and the impact oflow-temperature transistor performance variations on circuit designwas also analyzed.Based on the proposed cryogenic model,a 180 nmCMOS-based 450 to 850 MHz clock generator operating at 4 K forquantum computing applications was presented.At the output frequency of 600 MHz,it achieved<4.8 ps RMS jitter with 30 mWpower consumption(with test buffer),corresponding to a−211.6 dBjitter-power FOM,which is suitable for providing a stable clock signalfor the control and readout electronics of scalable quantum computers.展开更多
A novel monolithic digitalized random carrier frequency modulation spread-spectrum clock generator （RCF-SSCG） is proposed.In this design,the output frequency of the proposed RCF-SSCG changes with the intensity of th...A novel monolithic digitalized random carrier frequency modulation spread-spectrum clock generator （RCF-SSCG） is proposed.In this design,the output frequency of the proposed RCF-SSCG changes with the intensity of the capacitive charge and discharge current.Its analytical model is induced and the effect of the modulation parameters on the spread spectrum is numerically simulated and discussed.Compared with other works,this design has the advantages of small size,low power consumption and good robustness.The circuit has been fabricated in a 0.5μm CMOS process and applied to a class D amplifier in which the proposed RCF-SSCG occupies an area of 0.112 mm^2 and consumes 9 mW.The experimental results confirm the theoretical analyses.展开更多
A PLL clock generator with reconfigurable multi-functions for FPGA design applications is presented. This clock generator has two configurable operation modes to achieve clock multiplication and phase alignment functi...A PLL clock generator with reconfigurable multi-functions for FPGA design applications is presented. This clock generator has two configurable operation modes to achieve clock multiplication and phase alignment functions,respectively.The output clock signal has advanced clock shift ability such that the phase shift and duty cycle are programmable.In order to further improve the accuracy of phase alignment and phase shift,a VCO design based on a novel quick start-up technique is proposed.A new delay partition method is also adopted to improve the speed of the post-scale counter,which is used to realize the programmable phase shift and duty cycle.A prototype chip implemented in a 0.13-μm CMOS process achieves a wide tuning range from 270 MHz to 1.5 GHz.The power consumption and the measured RMS jitter at 1 GHz are less than 18 mW and 9 ps,respectively.The settling time is approximately 2μs.展开更多
This paper constructs the probability model of the multi-valued KM_1M_2 clock controlled generator,and discusses the probability distributing,homogeneous Markov property,ergodic property,strict placidity,numeral chara...This paper constructs the probability model of the multi-valued KM_1M_2 clock controlled generator,and discusses the probability distributing,homogeneous Markov property,ergodic property,strict placidity,numeral character and the property of large numbers of the random variables with this kind of output sequence.It gets the probability formula of the coincidence of the output sequence with the input sequence,and gives important reference to the design and analysis of the multi-valued key stream clock controlled generator in cryptography.展开更多
First the research is conducted on the design of the two-phase sinusoidal power clock generator in this paper. Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks--Clocked...First the research is conducted on the design of the two-phase sinusoidal power clock generator in this paper. Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks--Clocked Transmission Gate Adiabatic Logic （CTGAL） circuit is presented. This circuit makes use of the clocked transmission gates to sample the input signals, then the output loads are charged and discharged in a fully adiabatic manner by using bootstrapped N-Channel Metal Oxide Semiconductor （NMOS） and Complementary Metal Oxide Semiconductor （CMOS） latch structure. Finally, with the parameters of Taiwan Semiconductor Manufacturing Company （TSMC） 0.25um CMOS device, the transient energy consumption of CTGAL, Bootstrap Charge-Recovery Logic （BCRL） and Pass-transistor Adiabatic Logic （PAL） including their clock generators is simulated. The simulation result indicates that CTGAL circuit has the characteristic of remarkably low energy consumption.展开更多
The superconducting rapid single flux quantum(RSFQ)integrated circuit is a promising solu-tion for overcoming speed and power bottlenecks in high-performance computing systems in the post-Moore era.This paper presents...The superconducting rapid single flux quantum(RSFQ)integrated circuit is a promising solu-tion for overcoming speed and power bottlenecks in high-performance computing systems in the post-Moore era.This paper presents an architecture designed to improve the speed and power limitations of high-performance computing systems using superconducting technology.Since superconducting microprocessors,which operate at cryogenic temperatures,require support from semiconductor cir-cuits,the proposed design utilizes the von Neumann architecture with a superconducting RSFQ mi-croprocessor,cryogenic semiconductor memory,a room temperature field programmable gate array(FPGA)controller,and a host computer for input/output.Additionally,the paper introduces two key circuit designs:a start/stop controllable superconducting clock generator and an asynchronous communication interface between the RSFQ and semiconductor chips used to implement the control system.Experimental results demonstrate that the proposed design is feasible and effective,provi-ding valuable insights for future superconducting computer systems.展开更多
A new low power quasi adiabatic logic,complementary pass transistor adiabatic logic (CPAL),is presented.The CPAL circuit is driven by a new three phase power clock,and its non adiabatic loss on output loads can b...A new low power quasi adiabatic logic,complementary pass transistor adiabatic logic (CPAL),is presented.The CPAL circuit is driven by a new three phase power clock,and its non adiabatic loss on output loads can be effectively reduced by using complementary pass transistor logic and transmission gates.Furthermore,the minimization of the energy consumption can be obtained by choosing the optimal size of bootstrapped nMOS transistors,thus it has more efficient energy transfer and recovery.A three phase power supply generator with a small control logic circuit and a single inductor is proposed.An 8 bit adder based on CPAL is designed and verified.With MOSIS 0 25μm CMOS technology,the CPAL adder consumes only 35% of the dissipated energy of a 2N 2N2P adder and is about 50% of the dissipated energy of a PFAL adder for clock rates ranging from 50 to 200MHz.展开更多
A high speed sampler for a sub-sampling impulse radio UWB receiver is presented. In this design, the sampler uses a time-interleaved topology with a single track and hold circuit, full custom clock generator, and off-...A high speed sampler for a sub-sampling impulse radio UWB receiver is presented. In this design, the sampler uses a time-interleaved topology with a single track and hold circuit, full custom clock generator, and off- set cancelled comparator. These three main blocks are also discussed and analyzed. The circuit was fabricated in 0.13 μm CMOS technology. Measurement results indicate that the sampler achieves a maximum 3 GS/s sampling rate. The power consumption of the sampler is 27 mW under a supply voltage of 1.2 V. The total chip area including pads is 1.4 × 0.97 mm^2.展开更多
A time-domain digitally controlled oscillator （DCO） is proposed. The DCO is composed of a free-running ring oscillator （FRO） and a two lap-selectors integrated flying-adder （FA）. With a coiled cell array which a...A time-domain digitally controlled oscillator （DCO） is proposed. The DCO is composed of a free-running ring oscillator （FRO） and a two lap-selectors integrated flying-adder （FA）. With a coiled cell array which allows uniform loading capacitances of the delay cells, the FRO produces 32 outputs with consistent tap spacing for the FA as reference clocks. The FA uses the outputs from the FRO to generate the output of the DCO according to the control number, resulting in a linear dependence of the output period, instead of the frequency on the digital controlling word input. Thus the proposed DCO ensures a good conversion linearity in a time-domain, and is suitable for time-domain all-digital phase locked loop applications. The DCO was implemented in a standard 0.13μm digital logic CMOS process. The measurement results show that the DCO has a linear and monotonic tuning curve with gain variation of less than 10%, and a very low root mean square period jitter of 9.3 ps in the output clocks. The DCO works well at supply voltages ranging from 0.6 to 1.2 V, and consumes 4 mW of power with 500 MHz frequency output at 1.2 V supply voltage.展开更多
基金acknowledge the support from the National Natural Science Foundation of China(No.12034018)the Inno-vation Program for Quantum Science and Technology(No.2021ZD0302300).
文摘The development of large-scale quantum computing has boosted anurgent desire for the advancement of cryogenic CMOS(cryo-CMOS),which is a promising scalable solution for the control and read-out interface of quantum bits.In the current work,180 nm CMOS transistors were characterized and modeled down to 4 K,and the impact oflow-temperature transistor performance variations on circuit designwas also analyzed.Based on the proposed cryogenic model,a 180 nmCMOS-based 450 to 850 MHz clock generator operating at 4 K forquantum computing applications was presented.At the output frequency of 600 MHz,it achieved<4.8 ps RMS jitter with 30 mWpower consumption(with test buffer),corresponding to a−211.6 dBjitter-power FOM,which is suitable for providing a stable clock signalfor the control and readout electronics of scalable quantum computers.
基金Project supported by the National Natural Science Foundation of China(No.60436030).
文摘A novel monolithic digitalized random carrier frequency modulation spread-spectrum clock generator （RCF-SSCG） is proposed.In this design,the output frequency of the proposed RCF-SSCG changes with the intensity of the capacitive charge and discharge current.Its analytical model is induced and the effect of the modulation parameters on the spread spectrum is numerically simulated and discussed.Compared with other works,this design has the advantages of small size,low power consumption and good robustness.The circuit has been fabricated in a 0.5μm CMOS process and applied to a class D amplifier in which the proposed RCF-SSCG occupies an area of 0.112 mm^2 and consumes 9 mW.The experimental results confirm the theoretical analyses.
基金Project supported by the National High Technology Research and Development Program of China(No2008AA010701)
文摘A PLL clock generator with reconfigurable multi-functions for FPGA design applications is presented. This clock generator has two configurable operation modes to achieve clock multiplication and phase alignment functions,respectively.The output clock signal has advanced clock shift ability such that the phase shift and duty cycle are programmable.In order to further improve the accuracy of phase alignment and phase shift,a VCO design based on a novel quick start-up technique is proposed.A new delay partition method is also adopted to improve the speed of the post-scale counter,which is used to realize the programmable phase shift and duty cycle.A prototype chip implemented in a 0.13-μm CMOS process achieves a wide tuning range from 270 MHz to 1.5 GHz.The power consumption and the measured RMS jitter at 1 GHz are less than 18 mW and 9 ps,respectively.The settling time is approximately 2μs.
基金Supported by the Computer Network and Information Security Foundation of Ministry of Education Laboratory(20040108)
文摘This paper constructs the probability model of the multi-valued KM_1M_2 clock controlled generator,and discusses the probability distributing,homogeneous Markov property,ergodic property,strict placidity,numeral character and the property of large numbers of the random variables with this kind of output sequence.It gets the probability formula of the coincidence of the output sequence with the input sequence,and gives important reference to the design and analysis of the multi-valued key stream clock controlled generator in cryptography.
基金Supported by the National Natural Science Foundation of China (No. 60273093)the Natural Science Foundation of Zhejinag Province(No. Y104135) the Student Sci-entific Research Foundation of Ningbo university (No.C38).
文摘First the research is conducted on the design of the two-phase sinusoidal power clock generator in this paper. Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks--Clocked Transmission Gate Adiabatic Logic （CTGAL） circuit is presented. This circuit makes use of the clocked transmission gates to sample the input signals, then the output loads are charged and discharged in a fully adiabatic manner by using bootstrapped N-Channel Metal Oxide Semiconductor （NMOS） and Complementary Metal Oxide Semiconductor （CMOS） latch structure. Finally, with the parameters of Taiwan Semiconductor Manufacturing Company （TSMC） 0.25um CMOS device, the transient energy consumption of CTGAL, Bootstrap Charge-Recovery Logic （BCRL） and Pass-transistor Adiabatic Logic （PAL） including their clock generators is simulated. The simulation result indicates that CTGAL circuit has the characteristic of remarkably low energy consumption.
基金the Strategic Priority Research Program of Chinese Academy of Sciences(No.XDA18000000)the National Natural Science Foundation of China(No.61732018,61872335).
文摘The superconducting rapid single flux quantum(RSFQ)integrated circuit is a promising solu-tion for overcoming speed and power bottlenecks in high-performance computing systems in the post-Moore era.This paper presents an architecture designed to improve the speed and power limitations of high-performance computing systems using superconducting technology.Since superconducting microprocessors,which operate at cryogenic temperatures,require support from semiconductor cir-cuits,the proposed design utilizes the von Neumann architecture with a superconducting RSFQ mi-croprocessor,cryogenic semiconductor memory,a room temperature field programmable gate array(FPGA)controller,and a host computer for input/output.Additionally,the paper introduces two key circuit designs:a start/stop controllable superconducting clock generator and an asynchronous communication interface between the RSFQ and semiconductor chips used to implement the control system.Experimental results demonstrate that the proposed design is feasible and effective,provi-ding valuable insights for future superconducting computer systems.
文摘A new low power quasi adiabatic logic,complementary pass transistor adiabatic logic (CPAL),is presented.The CPAL circuit is driven by a new three phase power clock,and its non adiabatic loss on output loads can be effectively reduced by using complementary pass transistor logic and transmission gates.Furthermore,the minimization of the energy consumption can be obtained by choosing the optimal size of bootstrapped nMOS transistors,thus it has more efficient energy transfer and recovery.A three phase power supply generator with a small control logic circuit and a single inductor is proposed.An 8 bit adder based on CPAL is designed and verified.With MOSIS 0 25μm CMOS technology,the CPAL adder consumes only 35% of the dissipated energy of a 2N 2N2P adder and is about 50% of the dissipated energy of a PFAL adder for clock rates ranging from 50 to 200MHz.
基金supported by the National High Technology Research and Development Program of China(No.2009AA01Z261)the State Key Laboratory of Wireless Telecommunication,Southeast University.
文摘A high speed sampler for a sub-sampling impulse radio UWB receiver is presented. In this design, the sampler uses a time-interleaved topology with a single track and hold circuit, full custom clock generator, and off- set cancelled comparator. These three main blocks are also discussed and analyzed. The circuit was fabricated in 0.13 μm CMOS technology. Measurement results indicate that the sampler achieves a maximum 3 GS/s sampling rate. The power consumption of the sampler is 27 mW under a supply voltage of 1.2 V. The total chip area including pads is 1.4 × 0.97 mm^2.
文摘A time-domain digitally controlled oscillator （DCO） is proposed. The DCO is composed of a free-running ring oscillator （FRO） and a two lap-selectors integrated flying-adder （FA）. With a coiled cell array which allows uniform loading capacitances of the delay cells, the FRO produces 32 outputs with consistent tap spacing for the FA as reference clocks. The FA uses the outputs from the FRO to generate the output of the DCO according to the control number, resulting in a linear dependence of the output period, instead of the frequency on the digital controlling word input. Thus the proposed DCO ensures a good conversion linearity in a time-domain, and is suitable for time-domain all-digital phase locked loop applications. The DCO was implemented in a standard 0.13μm digital logic CMOS process. The measurement results show that the DCO has a linear and monotonic tuning curve with gain variation of less than 10%, and a very low root mean square period jitter of 9.3 ps in the output clocks. The DCO works well at supply voltages ranging from 0.6 to 1.2 V, and consumes 4 mW of power with 500 MHz frequency output at 1.2 V supply voltage.
