A three-terminal silicon-based light emitting device is proposed and fabricated in standard 0.35 μm complementary metal-oxide-semiconductor technology. This device is capable of versatile working modes： it can emit ...A three-terminal silicon-based light emitting device is proposed and fabricated in standard 0.35 μm complementary metal-oxide-semiconductor technology. This device is capable of versatile working modes： it can emit visible to near infra-red （NIR） light （the spectrum ranges from 500 nm to 1000 nm） in reverse bias avalanche breakdown mode with working voltage between 8.35 V-12 V and emit NIR light （the spectrum ranges from 900 nm to 1300 nm） in the forward injection mode with working voltage below 2 V. An apparent modulation effect on the light intensity from the polysilicon gate is observed in the forward injection mode. Furthermore, when the gate oxide is broken down, NIR light is emitted from the polysilicon/oxide/silicon structure. Optoelectronic characteristics of the device working in different modes are measured and compared. The mechanisms behind these different emissions are explored.展开更多
A 10 Gbit/s (STM-64, OC-192) 1:4 demultiplexer (DEMUX) with 4-phase clock wasachieved in TSMC's standard 0.25 μm complementary metal-oxide-semiconductor (CMOS) technique. Allof the circuits are in source coupled ...A 10 Gbit/s (STM-64, OC-192) 1:4 demultiplexer (DEMUX) with 4-phase clock wasachieved in TSMC's standard 0.25 μm complementary metal-oxide-semiconductor (CMOS) technique. Allof the circuits are in source coupled FET logic (SCFL) to achieve as high as possible speed andsuppress common mode distortions. This DEMUX is featured by constant-delay buffers to generate a4-phase clock and adjust skews of the four channel outputs. The fabricated DEMUX operates error freeat 10 Gbit/s by 2^(31) -1 pseudorandom bit sequences (PRBS) via on-wafer testing. The measured rootmean square (rms) jitter, rising and failing edge of the eye-diagram are 11, 123 and 137 ps,respectively. The chip size is 0.9 mm x 1.2 mm and the power dissipation is 550 mW with a 3. 3 Vsupply.展开更多
A fully integrated class-E power amplifier（PA） at 2.4 GHz implemented in a 0. 18 μm 6-metal-layer mixed/RF CMOS （ complementary metal-oxide-semiconductor transistor ） technology is presented. A two-stage amplific...A fully integrated class-E power amplifier（PA） at 2.4 GHz implemented in a 0. 18 μm 6-metal-layer mixed/RF CMOS （ complementary metal-oxide-semiconductor transistor ） technology is presented. A two-stage amplification structure is chosen for this PA. The driving stage produces a high swing switch signal by using resonation technology. The output stage is designed as a class-E topology to realize the power amplification. Under a 1.2 V power supply, the PA delivers a maximum output power of 8. 8 dBm with a power-added efficiency （PAE） of 44%. A new power control method for the class-E power amplifier is described. By changing the amplitude and duty cycle of the signal which enters the class-E switch transistor, the output power can be covered from - 3 to 8. 8 dBm through a three-bit control word. The proposed PA can be used in low power applications, such as wireless sensor networks and biotelemetry systems.展开更多
Radiation effects on complementary metal-oxide-semiconductor（CMOS） active pixel sensors（APS） induced by proton and γ-ray are presented. The samples are manufactured with the standards of 0.35 μm CMOS technology....Radiation effects on complementary metal-oxide-semiconductor（CMOS） active pixel sensors（APS） induced by proton and γ-ray are presented. The samples are manufactured with the standards of 0.35 μm CMOS technology. Two samples have been irradiated un-biased by 23 MeV protons with fluences of 1.43 × 10^11 protons/cm^2 and 2.14 × 10^11 protons/cm-2,respectively, while another sample has been exposed un-biased to 65 krad（Si） ^60Co γ-ray. The influences of radiation on the dark current, fixed-pattern noise under illumination, quantum efficiency, and conversion gain of the samples are investigated. The dark current, which increases drastically, is obtained by the theory based on thermal generation and the trap induced upon the irradiation. Both γ-ray and proton irradiation increase the non-uniformity of the signal, but the nonuniformity induced by protons is even worse. The degradation mechanisms of CMOS APS image sensors are analyzed,especially for the interaction induced by proton displacement damage and total ion dose（TID） damage.展开更多
Carbon nanotube field-effect transistors(CNTFETs)are increasingly recognized as a viable option for creating high-performance,low-power,and densely integrated circuits(ICs).Advancements in carbon-based electronics,enc...Carbon nanotube field-effect transistors(CNTFETs)are increasingly recognized as a viable option for creating high-performance,low-power,and densely integrated circuits(ICs).Advancements in carbon-based electronics,encompassing materials and device technology,have enabled the fabrication of circuits with over 1000 gates,marking carbon-based integrated circuit design as a burgeoning field of research.A critical challenge in the realm of carbon-based very-large-scale integration(VLSI)is the lack of suitable automated design methodologies and infrastructure platforms.In this study,we present the development of a waferscale 3μm carbon-based complementary metal-oxide-semiconductor(CMOS)process design kit(PDK)(3μm-CNTFETs-PDK)compatible with silicon-based Electronic Design Automation(EDA)tools and VLSI circuit design flow.The proposed 3μm-CNTFETs-PDK features a contacted gate pitch(CGP)of 21μm,a gate density of 128 gates/mm^(2),and a transistor density of 554 transistors/mm^(2),with an intrinsic gate delay around 134 ns.Validation of the 3μm-CNTFETs-PDK was achieved through the successful design and tape-out of 153 standard cells and 333-stage ring oscillator circuits.Leveraging the carbon-based PDK and a silicon-based design platform,we successfully implemented a complete 64-bit static random-access memory(SRAM)circuit system for the first time,which exhibited timing,power,and area characteristics of clock@10 kHz,122.1μW,3795μm×2810μm.This research confirms that carbon-based IC design can be compatible with existing EDA tools and silicon-based VLSI design flow,thereby laying the groundwork for future carbon-based VLSI advancements.展开更多
A Ka-band sub-harmonically pumped resistive mixer （SHPRM） was designed and fabricated using the standard 0.18-μm complementary metal-oxide-semiconductor （CMOS） technology. An area-effective asymmetric broadside c...A Ka-band sub-harmonically pumped resistive mixer （SHPRM） was designed and fabricated using the standard 0.18-μm complementary metal-oxide-semiconductor （CMOS） technology. An area-effective asymmetric broadside coupled spiral Marchand balance-to-unbalance （balun） with magnitude and phase imbalance compensation is used in the mixer to transform local oscillation （LO） signal from single to differential mode. The results showed that the SHPRM achieves the conversion gain of -15- -12.5 dB at fixed fIF=0.5 GHz with 8 dBm LO input power for the radio frequency （RF） bandwidth of 28 35 GHz. The in-band LO-intermediate freqency （IF）, RF-IF, and LO-RF isolations are better than 31, 34, and 36 dB, respectively. Besides, the 2LO-IF and 2LO-RF isolations are better than 60 and 45 dB, respectively. The measured input referred PIdB and 3rd-order inter-modulation intercept point （IIP3） are 0.5 and 10.5 dBm, respectively. The measurement is performed under a gate bias voltage as low as 0.1 V and the whole chip only occupies an area of 0.33 mm^2 including pads.展开更多
Metal-oxide-semiconductor field effect transistor(MOSFET) intrinsic gain degradation caused by channel length modulation(CLM) effect is examined.A simplified model based on Berkeley short-channel insulator-gate field ...Metal-oxide-semiconductor field effect transistor(MOSFET) intrinsic gain degradation caused by channel length modulation(CLM) effect is examined.A simplified model based on Berkeley short-channel insulator-gate field effect transistor model version 4(BSIM4) current expression for sub-100 nm MOSFET intrinsic gain is deduced,which only needs a few technology parameters.With this transistor intrinsic gain model,complementary metal-oxide-semiconductor(CMOS) operational amplifier(op amp) DC gain could be predicted.A two-stage folded cascode op amp is used as an example in this work.Non-minimum length device is used to improve the op amp DC gain.An improvement of 20 dB is proved when using doubled channel length design.Optimizing transistor bias condition and using advanced technology with thinner gate dielectric thickness and shallower source/drain junction depth can also increase the op amp DC gain.After these,a full op amp DC gain scaling roadmap is proposed,from 130 nm technology node to 32 nm technology node.Five scaled op amps are built and their DC gains in simulation roll down from 69.6 to 41.1 dB.Simulation shows transistors biased at higher source-drain voltage will have more impact on the op amp DC gain scaling over technology.The prediction based on our simplified gain model agrees with SPICE simulation results.展开更多
A composite ultraviolet （UV）/blue photode- tector structure has been proposed, which is composed of P-type silicon substrate, Pwelb Nwell and N-channel metal- oxide-semiconductor field-effect transistor （NMOSFET） ...A composite ultraviolet （UV）/blue photode- tector structure has been proposed, which is composed of P-type silicon substrate, Pwelb Nwell and N-channel metal- oxide-semiconductor field-effect transistor （NMOSFET） realized in the PweH. In this photodetector, lateral ring- shaped Pwell-Nwell junction was used to separate the photogenerated carriers, and non-equilibrium excess hole was injected to the Pwell bulk for changing the bulk potential and shifting the NMOSFET＇s threshold voltage as well as the output drain current. By technology computer-aided design （TCAD） device, simulation and analysis of this proposed photodetector were carried out. Simulation results show that the combined photodetector has enhanced responsivity to UV/blue spectrum. More- over, it exhibits very high sensitivity to weak and especially ultral-weak optical light. A sensitivity of 7000 A/W was obtained when an incident optical power of 0.01 μW was illuminated to the photodetector, which is 35000 times higher than the responsivity of a conventional silicon-based UV photodiode （usually is about 0.2 A/W）. As a result, this proposed combined photodetector has great potential values for UV applications.展开更多
A neuronal signal detecting circuit and a neuronal signal stimulating circuit designed for a monolithic integrated MEA（micro-electrode array） system are described. As a basic cell of the circuits, an OPA（ operation...A neuronal signal detecting circuit and a neuronal signal stimulating circuit designed for a monolithic integrated MEA（micro-electrode array） system are described. As a basic cell of the circuits, an OPA（ operational amplifier） is designed with low power, low noise, small size and high gain. The detecting circuit has a chip area of 290 μm × 400 μm, a power dissipation of 2.02 mW, an equivalent input noise of 17.72 nV/ Hz, a gain of 60. 5 dB, and an output voltage from - 2. 48 to ＋ 2. 5 V. The stimulating circuit has a chip area of 130 μm × 290 μm, a power dissipation of 740 μW, and an output voltage from - 2. 5 to 2. 04 V. The parameters show that two circuits are suitable for a monolithic integrated MEA system. The detecting circuit and MEA have been fabricated. The test results show that the detecting circuit works well.展开更多
Thanks to its single-atomic-layer structure,high carrier transport,and low power dissipation,carbon nanotube electronics is a leading candidate towards beyond-silicon technologies.Its low temperature fabrication proce...Thanks to its single-atomic-layer structure,high carrier transport,and low power dissipation,carbon nanotube electronics is a leading candidate towards beyond-silicon technologies.Its low temperature fabrication processes enable three-dimensional(3D)integration with logic and memory(static random access memory(SRAM),magnetic random access memory(MRAM),resistive random access memory(RRAM),etc.)to realize efficient near-memory computing.Importantly,carbon nanotube transistors require good thermal stability up to 400℃ processing temperature to be compatible with back-end-of-line(BEOL)process,which has not been previously addressed.In this work,we developed a robust wafer-scale process to build complementary carbon nanotube transistors with high thermal stability and good uniformity,where AlN was employed as electrostatic doping layer.The gate stack and passivation layer were optimized to realize high-quality interfaces.Specifically,we demonstrate 1-bit carbon nanotube full adders working under 250℃ with rail-to-rail outputs.展开更多
Growing a silicon(Si) layer on top of stacked Si-germanium(Ge) compressive layer can introduce a tensile strain on the former, resulting in superior device characteristics. Such a structure can be used for high perfor...Growing a silicon(Si) layer on top of stacked Si-germanium(Ge) compressive layer can introduce a tensile strain on the former, resulting in superior device characteristics. Such a structure can be used for high performance complementary metal-oxide-semiconductor(CMOS) circuits. Down scaling metal-oxide-semiconductor field-effect transistors(MOSFETs) into the deep submicron/nanometer regime forces the source(S) and drain(D) series resistance to become comparable with the channel resistance and thus it cannot be neglected. Owing to the persisting technological importance of strained Si devices, in this work, we propose a multi-iterative technique for evaluating the performance of strained-Si/strained-Si_(1-y)Ge_y/relaxed-Si_(1-x)Ge_x MOSFETs and its related circuits in the presence of S/D series resistance, leading to the development of a simulator that can faithfully plot the performance of the device and related digital circuits. The impact of strain on device/circuit performance is also investigated with emphasis on metal gate and high-k dielectric materials.展开更多
The compact full custom layout design of a 16 kbit mask-programmable complementary metal oxide semiconductor (CMOS) read only memory (ROM) with low power dissipation is introduced. By optimizing storage cell size and ...The compact full custom layout design of a 16 kbit mask-programmable complementary metal oxide semiconductor (CMOS) read only memory (ROM) with low power dissipation is introduced. By optimizing storage cell size and peripheral circuit structure, the ROM has a small area of 0.050 mm2 with a power-delay product of 0.011 pJ/bit at +1.8 V. The high packing density and the excellent power-delay product have been achieved by using SMIC 0.18 μm 1P6M CMOS technology. A novel and simple sense amplifier/driver structure is presented which restores the signal full swing efficiently and reduces the signal rising time by 2.4 ns, as well as the memory access time. The ROM has a fast access time of 8.6 ns. As a consequence, the layout design not only can be embedded into microprocessor system as its program memory, but also can be fabricated individually as ROM ASIC.展开更多
Developing a low-cost, room-temperature operated and complementary metal-oxide-semiconductor(CMOS)compatible visible-blind short-wavelength infrared(SWIR) silicon photodetector is of interest for security,telecommunic...Developing a low-cost, room-temperature operated and complementary metal-oxide-semiconductor(CMOS)compatible visible-blind short-wavelength infrared(SWIR) silicon photodetector is of interest for security,telecommunications, and environmental sensing. Here, we present a silver-supersaturated silicon(Si:Ag)-based photodetector that exhibits a visible-blind and highly enhanced sub-bandgap photoresponse. The visible-blind response is caused by the strong surface-recombination-induced quenching of charge collection for short-wavelength excitation, and the enhanced sub-bandgap response is attributed to the deep-level electrontraps-induced band-bending and two-stage carrier excitation. The responsivity of the Si:Ag photodetector reaches 504 mA · W^(-1) at 1310 nm and 65 m A · W^(-1) at 1550 nm under-3 V bias, which stands on the stage as the highest level in the hyperdoped silicon devices previously reported. The high performance and mechanism understanding clearly demonstrate that the hyperdoped silicon shows great potential for use in optical interconnect and power-monitoring applications.展开更多
基金Project supported by the National Natural Science Foundation of China(Grant Nos.60536030,61036002,60776024,60877035 and 61036009)National High Technology Research and Development Program of China(Grant Nos.2007AA04Z329 and 2007AA04Z254)
文摘A three-terminal silicon-based light emitting device is proposed and fabricated in standard 0.35 μm complementary metal-oxide-semiconductor technology. This device is capable of versatile working modes： it can emit visible to near infra-red （NIR） light （the spectrum ranges from 500 nm to 1000 nm） in reverse bias avalanche breakdown mode with working voltage between 8.35 V-12 V and emit NIR light （the spectrum ranges from 900 nm to 1300 nm） in the forward injection mode with working voltage below 2 V. An apparent modulation effect on the light intensity from the polysilicon gate is observed in the forward injection mode. Furthermore, when the gate oxide is broken down, NIR light is emitted from the polysilicon/oxide/silicon structure. Optoelectronic characteristics of the device working in different modes are measured and compared. The mechanisms behind these different emissions are explored.
文摘A 10 Gbit/s (STM-64, OC-192) 1:4 demultiplexer (DEMUX) with 4-phase clock wasachieved in TSMC's standard 0.25 μm complementary metal-oxide-semiconductor (CMOS) technique. Allof the circuits are in source coupled FET logic (SCFL) to achieve as high as possible speed andsuppress common mode distortions. This DEMUX is featured by constant-delay buffers to generate a4-phase clock and adjust skews of the four channel outputs. The fabricated DEMUX operates error freeat 10 Gbit/s by 2^(31) -1 pseudorandom bit sequences (PRBS) via on-wafer testing. The measured rootmean square (rms) jitter, rising and failing edge of the eye-diagram are 11, 123 and 137 ps,respectively. The chip size is 0.9 mm x 1.2 mm and the power dissipation is 550 mW with a 3. 3 Vsupply.
基金The National High Technology Research and Development Program of China(863 Program)(No.2007AA01Z2A7)
文摘A fully integrated class-E power amplifier（PA） at 2.4 GHz implemented in a 0. 18 μm 6-metal-layer mixed/RF CMOS （ complementary metal-oxide-semiconductor transistor ） technology is presented. A two-stage amplification structure is chosen for this PA. The driving stage produces a high swing switch signal by using resonation technology. The output stage is designed as a class-E topology to realize the power amplification. Under a 1.2 V power supply, the PA delivers a maximum output power of 8. 8 dBm with a power-added efficiency （PAE） of 44%. A new power control method for the class-E power amplifier is described. By changing the amplitude and duty cycle of the signal which enters the class-E switch transistor, the output power can be covered from - 3 to 8. 8 dBm through a three-bit control word. The proposed PA can be used in low power applications, such as wireless sensor networks and biotelemetry systems.
基金Project supported the National Natural Science Foundation of China(Grant No.11675259)the West Light Foundation of the Chinese Academy of Sciences(Grant Nos.XBBS201316,2016-QNXZ-B-2,and 2016-QNXZ-B-8)Young Talent Training Project of Science and Technology,Xinjiang,China(Grant No.qn2015yx035)
文摘Radiation effects on complementary metal-oxide-semiconductor（CMOS） active pixel sensors（APS） induced by proton and γ-ray are presented. The samples are manufactured with the standards of 0.35 μm CMOS technology. Two samples have been irradiated un-biased by 23 MeV protons with fluences of 1.43 × 10^11 protons/cm^2 and 2.14 × 10^11 protons/cm-2,respectively, while another sample has been exposed un-biased to 65 krad（Si） ^60Co γ-ray. The influences of radiation on the dark current, fixed-pattern noise under illumination, quantum efficiency, and conversion gain of the samples are investigated. The dark current, which increases drastically, is obtained by the theory based on thermal generation and the trap induced upon the irradiation. Both γ-ray and proton irradiation increase the non-uniformity of the signal, but the nonuniformity induced by protons is even worse. The degradation mechanisms of CMOS APS image sensors are analyzed,especially for the interaction induced by proton displacement damage and total ion dose（TID） damage.
基金The authors gratefully acknowledge fundings from the Strategic Priority Research Program of Chinese Academy of Sciences(CAS)(No.XDA0330401)CAS Youth Interdisciplinary Team(No.JCTD-2022-07).
文摘Carbon nanotube field-effect transistors(CNTFETs)are increasingly recognized as a viable option for creating high-performance,low-power,and densely integrated circuits(ICs).Advancements in carbon-based electronics,encompassing materials and device technology,have enabled the fabrication of circuits with over 1000 gates,marking carbon-based integrated circuit design as a burgeoning field of research.A critical challenge in the realm of carbon-based very-large-scale integration(VLSI)is the lack of suitable automated design methodologies and infrastructure platforms.In this study,we present the development of a waferscale 3μm carbon-based complementary metal-oxide-semiconductor(CMOS)process design kit(PDK)(3μm-CNTFETs-PDK)compatible with silicon-based Electronic Design Automation(EDA)tools and VLSI circuit design flow.The proposed 3μm-CNTFETs-PDK features a contacted gate pitch(CGP)of 21μm,a gate density of 128 gates/mm^(2),and a transistor density of 554 transistors/mm^(2),with an intrinsic gate delay around 134 ns.Validation of the 3μm-CNTFETs-PDK was achieved through the successful design and tape-out of 153 standard cells and 333-stage ring oscillator circuits.Leveraging the carbon-based PDK and a silicon-based design platform,we successfully implemented a complete 64-bit static random-access memory(SRAM)circuit system for the first time,which exhibited timing,power,and area characteristics of clock@10 kHz,122.1μW,3795μm×2810μm.This research confirms that carbon-based IC design can be compatible with existing EDA tools and silicon-based VLSI design flow,thereby laying the groundwork for future carbon-based VLSI advancements.
基金Project supported by the National Basic Research Program (973) of China (No. 2010CB327404)the National High-Tech R&D Program (863) of China (No. 2011AA10305)the National Natural Science Foundation of China (No. 60901012)
文摘A Ka-band sub-harmonically pumped resistive mixer （SHPRM） was designed and fabricated using the standard 0.18-μm complementary metal-oxide-semiconductor （CMOS） technology. An area-effective asymmetric broadside coupled spiral Marchand balance-to-unbalance （balun） with magnitude and phase imbalance compensation is used in the mixer to transform local oscillation （LO） signal from single to differential mode. The results showed that the SHPRM achieves the conversion gain of -15- -12.5 dB at fixed fIF=0.5 GHz with 8 dBm LO input power for the radio frequency （RF） bandwidth of 28 35 GHz. The in-band LO-intermediate freqency （IF）, RF-IF, and LO-RF isolations are better than 31, 34, and 36 dB, respectively. Besides, the 2LO-IF and 2LO-RF isolations are better than 60 and 45 dB, respectively. The measured input referred PIdB and 3rd-order inter-modulation intercept point （IIP3） are 0.5 and 10.5 dBm, respectively. The measurement is performed under a gate bias voltage as low as 0.1 V and the whole chip only occupies an area of 0.33 mm^2 including pads.
文摘Metal-oxide-semiconductor field effect transistor(MOSFET) intrinsic gain degradation caused by channel length modulation(CLM) effect is examined.A simplified model based on Berkeley short-channel insulator-gate field effect transistor model version 4(BSIM4) current expression for sub-100 nm MOSFET intrinsic gain is deduced,which only needs a few technology parameters.With this transistor intrinsic gain model,complementary metal-oxide-semiconductor(CMOS) operational amplifier(op amp) DC gain could be predicted.A two-stage folded cascode op amp is used as an example in this work.Non-minimum length device is used to improve the op amp DC gain.An improvement of 20 dB is proved when using doubled channel length design.Optimizing transistor bias condition and using advanced technology with thinner gate dielectric thickness and shallower source/drain junction depth can also increase the op amp DC gain.After these,a full op amp DC gain scaling roadmap is proposed,from 130 nm technology node to 32 nm technology node.Five scaled op amps are built and their DC gains in simulation roll down from 69.6 to 41.1 dB.Simulation shows transistors biased at higher source-drain voltage will have more impact on the op amp DC gain scaling over technology.The prediction based on our simplified gain model agrees with SPICE simulation results.
基金Acknowledgements This work was supported by the State Key Program of National Natural Science of China （Grant No. 61233010）, the National Natural Science Foundation of China （Grant No. 61274043）, and the Program for New Century Excellent Talents in University of Ministry of Education of China （NCET-11-0975）.
文摘A composite ultraviolet （UV）/blue photode- tector structure has been proposed, which is composed of P-type silicon substrate, Pwelb Nwell and N-channel metal- oxide-semiconductor field-effect transistor （NMOSFET） realized in the PweH. In this photodetector, lateral ring- shaped Pwell-Nwell junction was used to separate the photogenerated carriers, and non-equilibrium excess hole was injected to the Pwell bulk for changing the bulk potential and shifting the NMOSFET＇s threshold voltage as well as the output drain current. By technology computer-aided design （TCAD） device, simulation and analysis of this proposed photodetector were carried out. Simulation results show that the combined photodetector has enhanced responsivity to UV/blue spectrum. More- over, it exhibits very high sensitivity to weak and especially ultral-weak optical light. A sensitivity of 7000 A/W was obtained when an incident optical power of 0.01 μW was illuminated to the photodetector, which is 35000 times higher than the responsivity of a conventional silicon-based UV photodiode （usually is about 0.2 A/W）. As a result, this proposed combined photodetector has great potential values for UV applications.
基金The National Natural Science Foundation of China (No.90307013,90707005)the Natural Science Foundation of Jiangsu Province(No. BK2008032)Open Foundation of State Key Laboratory of Bio-Electronics of Southeast University
文摘A neuronal signal detecting circuit and a neuronal signal stimulating circuit designed for a monolithic integrated MEA（micro-electrode array） system are described. As a basic cell of the circuits, an OPA（ operational amplifier） is designed with low power, low noise, small size and high gain. The detecting circuit has a chip area of 290 μm × 400 μm, a power dissipation of 2.02 mW, an equivalent input noise of 17.72 nV/ Hz, a gain of 60. 5 dB, and an output voltage from - 2. 48 to ＋ 2. 5 V. The stimulating circuit has a chip area of 130 μm × 290 μm, a power dissipation of 740 μW, and an output voltage from - 2. 5 to 2. 04 V. The parameters show that two circuits are suitable for a monolithic integrated MEA system. The detecting circuit and MEA have been fabricated. The test results show that the detecting circuit works well.
基金the National Natural Science Foundation of China(No.61888102)the Beijing Municipal Science and Technology Commission(No.D171100006617002).
文摘Thanks to its single-atomic-layer structure,high carrier transport,and low power dissipation,carbon nanotube electronics is a leading candidate towards beyond-silicon technologies.Its low temperature fabrication processes enable three-dimensional(3D)integration with logic and memory(static random access memory(SRAM),magnetic random access memory(MRAM),resistive random access memory(RRAM),etc.)to realize efficient near-memory computing.Importantly,carbon nanotube transistors require good thermal stability up to 400℃ processing temperature to be compatible with back-end-of-line(BEOL)process,which has not been previously addressed.In this work,we developed a robust wafer-scale process to build complementary carbon nanotube transistors with high thermal stability and good uniformity,where AlN was employed as electrostatic doping layer.The gate stack and passivation layer were optimized to realize high-quality interfaces.Specifically,we demonstrate 1-bit carbon nanotube full adders working under 250℃ with rail-to-rail outputs.
文摘Growing a silicon(Si) layer on top of stacked Si-germanium(Ge) compressive layer can introduce a tensile strain on the former, resulting in superior device characteristics. Such a structure can be used for high performance complementary metal-oxide-semiconductor(CMOS) circuits. Down scaling metal-oxide-semiconductor field-effect transistors(MOSFETs) into the deep submicron/nanometer regime forces the source(S) and drain(D) series resistance to become comparable with the channel resistance and thus it cannot be neglected. Owing to the persisting technological importance of strained Si devices, in this work, we propose a multi-iterative technique for evaluating the performance of strained-Si/strained-Si_(1-y)Ge_y/relaxed-Si_(1-x)Ge_x MOSFETs and its related circuits in the presence of S/D series resistance, leading to the development of a simulator that can faithfully plot the performance of the device and related digital circuits. The impact of strain on device/circuit performance is also investigated with emphasis on metal gate and high-k dielectric materials.
文摘The compact full custom layout design of a 16 kbit mask-programmable complementary metal oxide semiconductor (CMOS) read only memory (ROM) with low power dissipation is introduced. By optimizing storage cell size and peripheral circuit structure, the ROM has a small area of 0.050 mm2 with a power-delay product of 0.011 pJ/bit at +1.8 V. The high packing density and the excellent power-delay product have been achieved by using SMIC 0.18 μm 1P6M CMOS technology. A novel and simple sense amplifier/driver structure is presented which restores the signal full swing efficiently and reduces the signal rising time by 2.4 ns, as well as the memory access time. The ROM has a fast access time of 8.6 ns. As a consequence, the layout design not only can be embedded into microprocessor system as its program memory, but also can be fabricated individually as ROM ASIC.
基金National Natural Science Foundation of China(NSFC)(51532007,61574124,61721005)
文摘Developing a low-cost, room-temperature operated and complementary metal-oxide-semiconductor(CMOS)compatible visible-blind short-wavelength infrared(SWIR) silicon photodetector is of interest for security,telecommunications, and environmental sensing. Here, we present a silver-supersaturated silicon(Si:Ag)-based photodetector that exhibits a visible-blind and highly enhanced sub-bandgap photoresponse. The visible-blind response is caused by the strong surface-recombination-induced quenching of charge collection for short-wavelength excitation, and the enhanced sub-bandgap response is attributed to the deep-level electrontraps-induced band-bending and two-stage carrier excitation. The responsivity of the Si:Ag photodetector reaches 504 mA · W^(-1) at 1310 nm and 65 m A · W^(-1) at 1550 nm under-3 V bias, which stands on the stage as the highest level in the hyperdoped silicon devices previously reported. The high performance and mechanism understanding clearly demonstrate that the hyperdoped silicon shows great potential for use in optical interconnect and power-monitoring applications.
