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A wideband low power low phase noise dual-modulus prescaler 被引量:2
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作者 雷雪梅 王志功 王科平 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2011年第2期130-136,共7页
This paper describes a novel divide-by-32/33 dual-modulus prescaler (DMP). Here, a new combination of DFF has been introduced in the DMP. By means of the cooperation and coordination among three types, DFF, SCL, TPS... This paper describes a novel divide-by-32/33 dual-modulus prescaler (DMP). Here, a new combination of DFF has been introduced in the DMP. By means of the cooperation and coordination among three types, DFF, SCL, TPSC, and CMOS static flip-flop, the DMP demonstrates high speed, wideband, and low power consumption with low phase noise. The chip has been fabricated in a 0.18μm CMOS process of SMIC. The measured results show that the DMP's operating frequency is from 0.9 to 3.4 GHz with a maximum power consumption of 2.51 mW under a 1.8 V power supply and the phase noise is -134.78 dBc/Hz at 1 MHz offset from the 3.4 GHz carrier. The core area of the die without PAD is 57 x 30 #m2. Due to its excellent performance, the DMP could be applied to a PLL-based frequency synthesizer for many RF systems, especially for multi-standard radio applications. 展开更多
关键词 dual-modulus prescaler WIDEBAND low power low phase noise frequency synthesizer multi-standard radio
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An improved fully integrated,high-speed,dual-modulus divider
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作者 孙峥 徐勇 +3 位作者 马光彦 石会 赵斐 林莹 《Journal of Semiconductors》 EI CAS CSCD 2014年第11期125-129,共5页
A fully integrated 2n/2n+1 dual-modulus divider in GHz frequency range is presented. The improved structure can make all separated logic gates embed into correlative D flip-flops completely. In this way, the complex ... A fully integrated 2n/2n+1 dual-modulus divider in GHz frequency range is presented. The improved structure can make all separated logic gates embed into correlative D flip-flops completely. In this way, the complex logic functions can be performed with a minimum number of devices and with maximum speed, so that lower power consumption and faster speed are obtained. In addition, the low-voltage bandgap reference needed by the frequency divider is specifically designed to provide a 1.0 V output. According to the design demand, the circuit is fabricated in 0.18 μm standard CMOS process, and the measured results show that its operating frequency range is 1.1- 2.5 GHz. The dual-modulus divider dissipates 1.1 mA from a 1.8 V power supply. The temperature coefficient of the reference voltage circuit is 8.3 ppm/℃ when the temperature varies from -40 to + 125 ℃. By comparison, the dual-modulus divide designed in this paper can possess better performance and flexibility. 展开更多
关键词 fully-integrated dual-modulus divider source-coupled logic (SCL) bandgap reference
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Design of Down Scalers in Mixed-Signal GHz Frequency Synthesizer 被引量:1
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作者 徐勇 王志功 +3 位作者 仇应华 李智群 胡庆生 闵锐 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2005年第9期1711-1715,共5页
An optimized method is presented to design the down scalers in a GHz frequency synthesizer. The down scalers are comprised of dual modulus prescaler (DMP) and programmable & pulse swallow divider,different methods ... An optimized method is presented to design the down scalers in a GHz frequency synthesizer. The down scalers are comprised of dual modulus prescaler (DMP) and programmable & pulse swallow divider,different methods of high frequency analog circuit and digital logical synthesis are adopted respectively. Using a DMP high speed, lower jitter and lower power dissipation are obtained,and output frequency of 133.0MHz of the DMP working at divide-by-8 shows an RMS jitter less than 2ps. The flexibility and reusability of the progrs, mmable divider is high;its use could be extended to many complicated frequency synthesizers. By comparison,it is a better design on performance of high-frequency circuit and good design flexibility. 展开更多
关键词 PLL frequency synthesizer dual-modulus prescaler PROGRAMMABLE pulse swallow divider
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A low power wide-band CMOS PLL frequency synthesizer for portable hybrid GNSS receiver 被引量:1
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作者 肖时茂 于云丰 +2 位作者 马成炎 叶甜春 殷明 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2010年第3期85-89,共5页
The design consideration and implementation of a CMOS frequency synthesizer for the portable hybrid global navigation satellite system are presented. The large tuning range is achieved by tuning curve compensation usi... The design consideration and implementation of a CMOS frequency synthesizer for the portable hybrid global navigation satellite system are presented. The large tuning range is achieved by tuning curve compensation using an improved VCO resonant tank, which reduces the power consumption and obtains better phase noise performance. The circuit is validated by simulations and fabricated in a standard 0.18 μm 1P6M CMOS process. Close-loop phase noise measured is lower than -95 dBc at 200 kHz offset while the measured ttming range is 21.5% from 1.47 to 1.83 GHz. The proposed synthesizer including source coupled logic prescaler consumes 6.2 mA current from 1.8 V supply. The whole silicon required is only 0.53 mm2. 展开更多
关键词 CMOS GNSS dual-modulus voltage-controlled oscillator frequency synthesizer
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A 5-GHz programmable frequency divider in 0.18-μm CMOS technology
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作者 舒海涌 李智群 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2010年第5期85-89,共5页
A 5-GHz CMOS programmable frequency divider whose modulus can be varied from 2403 to 2480 for 2.4-GHz ZigBee applications is presented.The divider based on a dual-modulus prescaler(DMP) and pulse-swallow counter is ... A 5-GHz CMOS programmable frequency divider whose modulus can be varied from 2403 to 2480 for 2.4-GHz ZigBee applications is presented.The divider based on a dual-modulus prescaler(DMP) and pulse-swallow counter is designed to reduce power consumption and chip area.Implemented in the 0.18-μm mixed-signal CMOS process,the divider operates over a wide range of 1-7.4 GHz with an input signal of 7.5 dBm;the programmable divider output phase noise is -125.3 dBc/Hz at an offset of 100 kHz.The core circuit without test buffer consumes 4.3 mA current from a 1.8 V power supply and occupies a chip area of approximately 0.015 mm^2.The experimental results indicate that the programmable divider works well for its application in frequency synthesizers. 展开更多
关键词 frequency divider dual-modulus prescaler pulse-swallow frequency synthesizer
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A 900 MHz fractional-N synthesizer for UHF transceiver in 0.18μm CMOS technology
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作者 毛旭瑞 黄北举 陈弘达 《Journal of Semiconductors》 EI CAS CSCD 2014年第12期94-100,共7页
A 900 MHz fractional-N synthesizer is designed for the UHF transceiver. The VCO with a 4 bits capacitor bank covers 823–1061 MHz that implements 16(2^4)sub-bands. A 7/8 dual-modulus prescaler is implemented with a ... A 900 MHz fractional-N synthesizer is designed for the UHF transceiver. The VCO with a 4 bits capacitor bank covers 823–1061 MHz that implements 16(2^4)sub-bands. A 7/8 dual-modulus prescaler is implemented with a phase-switching circuit and high-speed flip–flops, which are composed of source coupled logic. The proposed synthesizer phase-locked loop is demonstrated with a 50 k Hz band width by a low 12.95 MHz reference clock, and offers a better phase noise and band width tradeoff. To reduce the out-band phase noise, a 4-levels 3-order single-loop sigma–delta modulator is applied. When its relative frequency resolution is settled to 10^-6, the testing results show that the phase noises are –120.6 dBc/Hz at 1 MHz and –95.0 dBc/Hz at 100 k Hz. The chip is2.1 mm^2 in UMC 0.18μm CMOS. The power is 36 m W at a 1.8 V supply. 展开更多
关键词 UHF RFID reader frequency synthesizer VCO 7/8 dual-modulus prescaler △Σ modulator
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A 4 GHz quadrature output fractional-N frequency synthesizer for an IR-UWB transceiver
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作者 郭诗塔 黄鲁 +2 位作者 袁海泉 冯立松 刘志明 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2010年第3期74-79,共6页
This paper describes a 4 GHz fractional-N frequency synthesizer for a 3.1 to 5 GHz IR-UWB transceiver. Designed in a 0.18μm mixed-signal & RF 1P6M CMOS process, the operating range of the synthesizer is 3.74 to 4.44... This paper describes a 4 GHz fractional-N frequency synthesizer for a 3.1 to 5 GHz IR-UWB transceiver. Designed in a 0.18μm mixed-signal & RF 1P6M CMOS process, the operating range of the synthesizer is 3.74 to 4.44 GHz. By using an 18-bit third-order ∑-△ modulator, the synthesizer achieves a frequency resolution of 15 Hz when the reference frequency is 20 MHz. The measured amplitude mismatch and phase error between I and Q signals are less than 0.1 dB and 0.8° respectively. The measured phase noise is -116 dBc/Hz at 3 MHz offset for a 4 GHz output. Measured spurious tones are lower than -60 dBc. The settling time is within 80°s. The core circuit conupSigmaes only 38.2 mW from a 1.8 V power supply. 展开更多
关键词 frequency synthesizer dual-modulus prescaler ∑-△ modulator QVCO
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